Abstract: A filter includes a capacitor (1) connected between the input end IN and the output end OUT of signals and constant current circuits (2, 3) of MOS structure connected between the power source VDD and the ground, and by connecting the output side node of the capacitor (1) and the intermediate node of the constant current circuits (2, 3). Thus, the cut-off frequency of the filter is reduced by adjusting the value of a current passed through the constant current circuits (2, 3), instead of increasing the circuit area required by using a capacitor having a large capacitance value or a resistor having a large resistance value.

Abstract: A two-way CATV system where a center device (1) and a cable modem (8) are connected via a CATV line (7) comprises a hard disc drive (11) for recording TV broadcasting programs transmitted from the center device (1) to the cable modem (8) via the CATV line (7). An e-mail transmitted over the Internet (5) to the center device (1) is transmitted to the cable modem (8) via the CATV line (7). The cable modem (8) analyzes the content of the e-mail to execute the processing specified by this e-mail, so that recording of TV broadcasting programs, download of digital contents, etc. with the CATV can be remotely operated from outside where a user stays with an internet-compatible portable information terminal.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device mountable with high density, which includes a simplified process but is capable of reducing a defect rate. A plurality of semiconductor chips of different kinds (processor chip and memory chip) are formed on a semiconductor wafer, and a go/no-go test is conducted on all the chips. The semiconductor wafer is cut and divided into pieces that each consist of a good processor chip and a good memory chip, and they are mounted on a substrate to form a semiconductor module.

Abstract: A digital-to-analog converter for generating output waveforms with less distortion without the need for high-speed components. The digital-to-analog converter comprises four data holding sections, four step function generators, an adding section, a D/A converter, two integrators and a timing controller. Four digital data successively inputs are held in the data holding sections, respectively, and the step function generators generate step function whose values corresponding to the held data. The adding section sums the step functions generated in the step function generators, and the D/A converter generates the analog stepwise voltage corresponding to the summed value. The two integrators integrate this combined waveform two times, thus producing a continuous analog voltage that connects the input digital data smoothly.

Abstract: A sampling function generator capable of providing continuous output corresponding to a sampling function. The sampling function generator 1 comprises a B spline function generation circuit 10, delay circuits 12 and 14, inverting amplifiers 16 and 18, and adding circuits 20 and 22. The B-spline function generation circuit 10 continuously produces signal waveforms according to a third order B spline function. After delayed by predetermined time or attenuated to 1/4 amplitude and inverted, the signal waveforms are combined in the adding circuits 20 and 22 to form a signal waveforms of a sampling function that is differentiable once over the range and has values of local support.

Abstract: The present invention intends to form bumps of desired size and shape by simple steps. For this end, pads 2 are formed on a printed circuit board 1 at the same space as pads on a semiconductor chip 5. Then, the entire upper surface of the printed circuit board 1 is covered with a resist 3 except pad formed areas. The surface of the printed circuit board 1 covered with the resist 3 is then oriented downwardly and is sprayed with molten solder from the bottom side. The molten solder attaches the pad formed surface on the printed circuit board 1 and ideal semispherical bumps 4 are formed by the influence of gravity. The printed circuit board 1 formed with the bumps 4 is aligned with the pads 6 on the semiconductor chip 5 to be transferred into a high temperature oven. The bumps 4 are molten for jointing the semiconductor chip 5 and the printed circuit board 1.

Abstract: A semiconductor device which is mounted with a plurality of semiconductor chips. The fraction defective is low when the device is manufactured, and the efficiency of inspection is high. A method for manufacturing such a semiconductor device is also disclosed. A plurality of kinds of semiconductor chips 1 are COB-mounted on a substrate 2 and the surface of the substrate 2 mounted with the chips 1 is encapsulated with a resin 3. Then all the chips 1 mounted on the substrate 2 are inspected at once. Semiconductor devices 10 are produced by cutting the substrate 2 into pairs of adjacently arranged two different kinds of semiconductor chips 1 together which are judged to be nondefective chips.

Abstract: A semiconductor device which is mounted with a plurality of semiconductor chips. The fraction defective is low when the device is manufactured, and the efficiency of inspection is high. A method for manufacturing such a semiconductor device is also disclosed. A plurality of identical bare chips 1 for memory are COB-mounted on a substrate 2, and the surface of the substrate 2 mounted with the chips 1 is encapsulated with a resin 3. Then all the chips 1 mounted on the substrate 2 are inspected at once. Four-chip, two-chip, and one-chip memory modules 10 are produced by cutting the substrate 2 and combining bare chips 1 which are judged to be nondefective chips.

Abstract: An object of the present invention is to provide a memory module capable of being mounted easily on various memory boards or mother boards, having a large memory capacity, and requiring a small mounting area. The memory module 10 includes four memory bare chips 1 scribed from a semiconductor wafer and mounted on a module board 2 by the COB technology. The module board 2 is formed with a row of pads 4 near the center portion in the longitudinal direction of the module board 2. Two memory bare chips 1 are disposed on the module board 2 at opposite sides of the pads 4. Each memory bare chip 1 is formed with pads 3 along the center line and the pads 3 are connected to the pads 4 on the module board 2 by the use of bonding wires 5. The bonding wires 5 and the memory bare chips 1 are covered with a plastic resin 6. Also, the module board 2 is formed with external connection terminals 8 on the outer side edges for connection to a memory board or a mother board by the LCC technology.