Patents Assigned to Nippon Electric Co., Ltd.
  • Publication number: 20200012042
    Abstract: An optical fiber manufacturing method includes setting a first holding member and a rod inside a glass pipe, the first holding member made of glass and having plural holes formed, so that the rod is supported by the first holding member; filling glass particles between the rod and a glass pipe inner wall; holding the rod such that the rod and the filled glass particles are enclosed by the glass pipe inner wall and the first and second holding members, and sealing one end of the glass pipe and manufacturing an intermediate; and manufacturing an optical fiber from the intermediate, wherein a bulk density of the first and second holding members is set with reference to a bulk density of a filling portion made from the glass particles, and the predetermined range is determined according to a core diameter permissible variation range in its longitudinal direction.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Applicants: FURUKAWA ELECTRIC CO., LTD., NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Shinichi ARAI, Harumi Inaba, Shigeto Matsumoto, Takeshi Yagi, Shinichi Aozasa, Kyozo Tsujikawa, Kazuhide Nakajima
  • Patent number: 10498079
    Abstract: An electronic device unit includes a circuit board having: a sealing resin portion in which a region in which an electronic component is mounted is sealed by a sealing resin; and a board end portion exposed from a side of the sealing resin portion. A plurality of connection terminals are provided on the board end portion so as to be aligned in a direction of the side of the sealing resin portion, and a resin portion thicker than the board end portion and having a wall-like projection shape is provided at at least one of side surfaces of the board end portion in the direction of the side. The resin portion is integrally molded with the sealing resin portion of the circuit board and a side surface of the resin portion is press-fitted into an insertion chamber of a connector.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 3, 2019
    Assignees: Mitsubishi Electric Corporation, NIPPON TANSHI CO., LTD.
    Inventors: Fumiaki Arimai, Hiroyoshi Nishizaki, Shinya Enomoto, Osamu Nishimura, Masaru Fujino
  • Publication number: 20190334284
    Abstract: An electronic device unit includes a circuit board having: a sealing resin portion in which a region in which an electronic component is mounted is sealed by a sealing resin; and a board end portion exposed from a side of the sealing resin portion. A plurality of connection terminals are provided on the board end portion so as to be aligned in a direction of the side of the sealing resin portion, and a resin portion thicker than the board end portion and having a wall-like projection shape is provided at at least one of side surfaces of the board end portion in the direction of the side. The resin portion is integrally molded with the sealing resin portion of the circuit board and a side surface of the resin portion is press-fitted into an insertion chamber of a connector.
    Type: Application
    Filed: November 30, 2018
    Publication date: October 31, 2019
    Applicants: Mitsubishi Electric Corporation, NIPPON TANSHI CO., LTD.
    Inventors: Fumiaki ARIMAI, Hiroyoshi NISHIZAKI, Shinya ENOMOTO, Osamu NISHIMURA, Masaru FUJINO
  • Publication number: 20130169920
    Abstract: Provided are a method for manufacturing a liquid crystal lens which, even with the use of a thin sheet glass as a glass sheet for dividing a liquid crystal layer, can reduce the likelihood of breakage of the thin sheet glass in the production process and the liquid crystal lens. A mother liquid crystal lens having a plurality of liquid crystal lens units arrayed in a longitudinal direction thereof is cut for each of the liquid crystal lens units to separate out the liquid crystal lens units and thus manufacture respective liquid crystal lenses 10. Longitudinally extending side surfaces 13c, 13d, 14c, and 14d of glass ribbons which provide thin sheet glasses 13 and 14 have an outwardly bulging curved shape in a cross section perpendicular to the longitudinal direction.
    Type: Application
    Filed: January 26, 2012
    Publication date: July 4, 2013
    Applicant: NIPPON ELECTRIC CO., LTD.
    Inventor: Masanori Wada
  • Publication number: 20100209648
    Abstract: A laminated glass (10) has a structure in which seven sheet glasses (20) and six PVB resin layers (30) are laminated alternately. A laminated region from a transparent surface (10a) on one side to 4.0 mm comprises two 0.7 mm-thick glass layers formed of two sheet glasses (20), one 0.8 mm-thick glass layer formed of the portion (20c) of one 1.5 mm-thick sheet glass (20) positioned in the laminated region, and two adhesion layers (30) with thicknesses of 1.3 mm and 0.5 mm. Each of the adhesion layers is interposed between the glass layers and is adhered to the glass layers. The laminated region with a depth of 4.0 mm from a transparent surface (10b) on the other side also has the same laminated structure as that in the above laminated region.
    Type: Application
    Filed: September 25, 2008
    Publication date: August 19, 2010
    Applicant: NIPPON ELECTRIC CO., LTD
    Inventors: Narutoshi Shimatani, Seiji Hamada
  • Patent number: 4951111
    Abstract: An integrated circuit device includes insulated-gate field effect transistors employing a semiconductor gate electrode used as a logic element. Part of the input interconnection layer serves as the semiconductor gate electrode and orthogonally intersects with a conductive layer. The logic circuits are interconnected to constitute a random gate logic circuit that can be operated at high speeds and formed with a high density.
    Type: Grant
    Filed: January 3, 1985
    Date of Patent: August 21, 1990
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hirohiko Yamamoto
  • Patent number: 4882616
    Abstract: A color filter, particularly a color filter for a solid state imaging device, comprising a dyeable resin layer, a plurality of variously colored dyed-areas formed in the dyeable resin layer, a plurality of non-dyed areas separating the dyed area from each other in the dyeable resin layer, and a plurality of photo-interception areas formed on the non-dyed areas is disclosed. The dyed areas are generally separated from each other by a distance greater than the diffusion length generated during dyeing or heat treatment. The dyed areas can also be spread under the photo-interception areas by a distance substantially equal to the diffusion length generated during dyeing or heat treatment.
    Type: Grant
    Filed: June 8, 1988
    Date of Patent: November 21, 1989
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Daisuke Manabe
  • Patent number: 4862173
    Abstract: A succession of input signals supplied to a quantizer is processed at sampling instants into a succession of quantized codes by step sizes with a current one of the quantized codes produced at each sampling instant with reference to a current step size adaptively decided not only by a next previous quantized code and a next previous step size but also by a reference size which is determined in accordance with an average level derived from a plurality of prior quantized codes produced until production of the next previous quantized code. A decoder decodes the quantized code succession into a reproduction of the quantizer input signal succession with each quantized code decoded with reference to a similarly adaptively decided step size. It is possible that the reference step size to be determined in a digital fashion as one of a few predetermined sizes or in an analog manner to be variable between two predetermined reference sizes.
    Type: Grant
    Filed: May 1, 1986
    Date of Patent: August 29, 1989
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Takao Nishitani
  • Patent number: 4857001
    Abstract: An electrical connector having contact elements, for mounting a leadless circuit board to a mother board. Each contact element is provided with a projection laterally projecting therefrom which engages with the lower opening edge of a through-hole of the mother board to maintain the connector in contact with the surface of the mother board. Connector apertures are arranged to a zigzag pattern to form first and second rows, and the contact elements are inserted in the apertures of the first and second rows with reversed orientation.
    Type: Grant
    Filed: April 6, 1988
    Date of Patent: August 15, 1989
    Assignees: Nippon Telegraph & Telephone Public Corporation, Nippon Electric Co., Ltd., Japan Aviation Electronics Industry Limited
    Inventors: Kenichi Nakano, Yoshihiro Umezawa, Tetsuro Tokaichi, Yoshiaki Ichimura, Natsuki Kawabe
  • Patent number: 4799101
    Abstract: A high-density integrated circuit employing different first and second channel types of insulated gate field effect transistors is disclosed, which comprises at least three stacked wiring layers, the lowest layer being formed of polycrystalline silicon and including silicon gates of the transistors, one of the upper layers being formed of polycrystalline silicon and used for feeding a power supply to some of the transistors and being connected to at least one well region on which the first channel type of transistors are formed, and the other of the upper layers being formed of high-conductivity metal.
    Type: Grant
    Filed: December 23, 1986
    Date of Patent: January 17, 1989
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hirotugu Eguchi
  • Patent number: 4786523
    Abstract: In a wired substrate, a conductive pattern is formed of an alloy of gold, a base metal, and a noble metal and is contiguous to an insulating layer of a mixture of oxides of the base and the noble metals. The alloy preferably includes the base and the noble metals to a total amount of 0.2 to 2 percent by weight. More preferably, the base metal is titanium, aluminum, or copper. The noble metal is palladium, ruthenium, rhodium, or nickel. The wired substrate is manfactured by forming a first layer of the base metal, a second layer of the noble metal, and a selectively formed gold layer successively on the substrate and by heat treating at least the first, the second, and the gold layers to convert the gold layer and those portions of the first and the second layers on which the gold layer is formed, to the conductive pattern and to concurrently convert other portions of the first and the second layers to the insulating layer. The first, the second, and the gold layers are preferably 0.025 to 0.4, 0.025 to 0.
    Type: Grant
    Filed: December 9, 1986
    Date of Patent: November 22, 1988
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Akihiro Dohya
  • Patent number: 4758834
    Abstract: A pager receiver for a radio calling signal carrying a call number and/or a message comprises a processing unit for producing a drive and an information signal to produce ordinary tone or tones related to the call number and to provide ordinary visual displays representative of the message, respectively. A processed signal is produced by the processing unit to provide extraordinary tones peculiar to a message-absent call, a message-present call, and a repeat call for repeatedly displaying a prior message. The processed signal also appears to provide extraordinary visual displays unique to the message-absent call. When the pager receiver has a plurality of preassigned call numbers, the processed signal is produced to provide such extraordinary displays inherent to each of the respective preassigned call numbers. In addition to the extraordinary displays of the preassigned call number, a plurality of messages are successively stored in a memory in a predetermined order to be successively displayed one by one.
    Type: Grant
    Filed: June 19, 1986
    Date of Patent: July 19, 1988
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Yukio Sato, Yoshio Ichikawa
  • Patent number: 4744082
    Abstract: A multiplexing communication system for combining several asynchronous digital signals 151, 156 into a single high-speed line 141 comprising synchronizing circuits 101, 106 on each on n input data lines, service information insertion circuits 180 on each of the n synchronized lines, an nBmB coder 130 utilizing a pulse stuffing circuit 170 for increasing the n synchronized signals to m synchronized signals, and a multiplexer 140 for converting the m synchronized signals into a single high speed output 141.
    Type: Grant
    Filed: March 8, 1983
    Date of Patent: May 10, 1988
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Hiroshi Fujimura, Kiyoaki Kawai
  • Patent number: 4727484
    Abstract: A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory (MMU), the other for storing a portion of the operand data located in main memory. A separate translation look aside buffer (TLB) is connected to each cache memory, with the TLB connected to the cache memory storing instructions operating to translate logical addresses to real addresses in the MMU storing instructions, while the TLB connected to the cache memory storing operand data operating to translate logical addresses to real addresses in the MMU storing operand data.
    Type: Grant
    Filed: December 24, 1986
    Date of Patent: February 23, 1988
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Masato Saito
  • Patent number: 4725876
    Abstract: A semiconductor device comprising at least two pinch resistors or two ion-implanted resistors having a precise resistance ratio therebetween. The pinch resistor and ion-implanted resistor have at least one region contributing to the determination of a resistance value, respectively. In two pinch resistors or two ion-implanted resistors, a ratio in number of a plurality of regions in one resistor to at least one region in the other resistor is selected to be identical to the resistance ratio of one resistor to the other resistor, resulting in that a precise resistance ratio is realized despite different configurations of the two resistors.
    Type: Grant
    Filed: May 15, 1986
    Date of Patent: February 16, 1988
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Jun Kishi
  • Patent number: 4717846
    Abstract: An output circuit protected by an abnormal voltage supplied at an output terminal is disclosed. The output circuit comprises a first switching circuit includes first and second transistors connected in series for providing an output terminal with a first potential therethrough in response to a first logic state of a logic signal, a second switching circuit for providing the output terminal with a second potential in response to a second logic state of the logic signal, and means for making the first and second transistors non-conducting when the first switching circuit is disenabled.
    Type: Grant
    Filed: September 25, 1986
    Date of Patent: January 5, 1988
    Assignee: Nippon Electric Co. Ltd.
    Inventor: Manabu Ando
  • Patent number: 4710136
    Abstract: A structure for mounting an electronic apparatus comprises a pair of opposed side members each having front and rear ends for guiding the apparatus between the front and rear ends of the structure. A rear member has a coupling element for establishing an electrical connection with the electronic apparatus. To make the apparatus retractable with a minimum of effort, the rear member is arranged to movably engage the side members so that when the apparatus is removed from the structure, the rear member is also moved with it, over a predetermined distance, allowing the apparatus to be more firmly gripped for further removal with a greater force that is sufficient to disengage the coupling elements from each other.
    Type: Grant
    Filed: April 11, 1985
    Date of Patent: December 1, 1987
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Takeshi Suzuki
  • Patent number: 4706107
    Abstract: A semiconductor memory device has a semiconductor substrate with a first semiconductor region of one conductivity type in the substrate. A second semiconductor region of the opposite conductivity type is formed in the first semiconductor region. A third semiconductor region of the opposite conductivity type is arranged to be in contact with the first semiconductor region. A fourth semiconductor region of the one conductivity type is formed in the third semiconductor region. A fifth semiconductor region of the one conductivity type, within the semiconductor substrate, has a concentration which is higher than the impurity concentration of the first semiconductor region and is provided under the third semiconductor region. A continuous gate electrode is provided via a gate insulating layer formed on the surface of the first semiconductor region and on the surface of the third semiconductor region.
    Type: Grant
    Filed: February 20, 1986
    Date of Patent: November 10, 1987
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Kazuo Terada, Susumu Kurosawa, Shunichi Suzuki
  • Patent number: 4704608
    Abstract: A pager receiver for a radio calling signal carrying a call number and/or a message comprises a processing unit for producing a drive and an information signal to produce ordinary tone or tones related to the call number and to provide ordinary visual displays representative of the message, respectively. A processed signal is produced by the processing unit to provide extraordinary tones peculiar to a message-absent call, a message-present call, and a repeat call for repeatedly displaying a prior message. The processed signal also appears to provide extraordinary visual displays unique to the message-absent call. When the pager receiver has a plurality of preassigned call numbers, the processed signal is produced to provide such extraordinary displays inherent to each of the respective preassigned call numbers. In addition to the extraordinary displays of the preassigned call number, a plurality of messages are successively stored in a memory in a predetermined order to be successively displayed one by one.
    Type: Grant
    Filed: July 21, 1986
    Date of Patent: November 3, 1987
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Yukio Sato, Yoshio Ichikawa
  • Patent number: RE32749
    Abstract: In a pattern display system wherein color signals are produced based on serial color data signals of red, green and blue and background colors from background color information storage means and a color pattern is displayed on predetermined picture elements in response to the color signals and an output of a voltage level signal generating circuit, there is provided color control information storage means, and amplitudes of the voltage level signal and the color signal are controlled by color control information from the storage means, so that the color pattern display can be effected with deep, pale, bright and dark properties of color controlled.
    Type: Grant
    Filed: November 19, 1984
    Date of Patent: September 13, 1988
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Toshio Ohura