Patents Assigned to Nippon Electric Co., Ltd.
  • Patent number: 4551908
    Abstract: A process of forming electrodes and interconnections in a silicon semiconductor device comprises the steps of forming an insulating film on a silicon substrate, defining an opening in the insulating film, depositing a layer of metal having a high melting point on the insulating film, implanting ions to mix an interface between the metal layer and the silicon substrate, heating the construction in a temperature in the range of from 400 to 650 degrees Celsius to form a silicide of the metal layer in the opening, and selectively etching away an unreacted metal layer so as to self-align the silicide metal layer with the opening. The silicide metal layer is then annealed in a non-reducing gas atmosphere at a temperature ranging from 800 to 1,100 degrees Celsius.
    Type: Grant
    Filed: October 2, 1984
    Date of Patent: November 12, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Eiji Nagasawa, Hidekazu Okabayashi, Mitsutaka Morimoto, Kohei Higuchi
  • Patent number: 4551767
    Abstract: A television signal transmission system with stationary-picture transmission capabilities including the ability to stop picture transmission at any point within a picture frame. The picture stop feature is realized by inserting a control code within each horizontal scanning interval. The control code signals any of several instructions, including start, stop, scan and line control header instructions. The stop control code is generated in the horizontal scanning interval corresponding to the stop point in the frame transmission to thereby inhibit further picture transmission. Picture transmission is restarted by the generation of a scan control code.
    Type: Grant
    Filed: January 31, 1983
    Date of Patent: November 5, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Toshiaki Higashiguchi, Michiaki Sonoda
  • Patent number: 4550982
    Abstract: Between a display electrode and a counter electrode, an all-solid-state organic electrochromic display device comprises a polymer layer comprising at least one organic electrochromic material and at lest one ionic material. The layer may be a polymer film of at least one polymer material in which film the electrochromic and the ionic materials are dispersed, a polymer electrochromic film comprising the electrochromic material in which film the ionic material is dispersed, a polymer ionic film comprising the ionic material in which film the electrochromic material is dispersed, or a polymer electrochromic and ionic film comprising the electrochromic and the ionic materials. Between the electrochromic layer and the counter electrode, the device may comprise a polymer redox layer which is similar in structure to the electrochromic layer and preferably comprises at least one ionic material.
    Type: Grant
    Filed: November 9, 1982
    Date of Patent: November 5, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Yoshihiko Hirai
  • Patent number: 4550307
    Abstract: A pulse generator for use in a digital/analog converter which generates a pulse train with pulse widths modulated in accordance with an input digital signal. The leading edge of an arbitrary pulse in the pulse train is widened by one half of a clock period and the trailing edge of another pulse is widened by one half of the clock period, in accordance with the input digital signal.
    Type: Grant
    Filed: January 14, 1983
    Date of Patent: October 29, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Mineo Akashi, Yoshitaka Kitada
  • Patent number: 4550390
    Abstract: A semiconductor memory having a construction making it less susceptible to .alpha.-rays. The memory includes a pair of transistors connected in a flip-flop arrangement. In each memory transistor there is a buried region of high concentration which contacts the collector region of the same impurity. The base region consists of a relatively low concentration part, in which the emitter or emitters are formed, and a high concentration part, to which the base electrode is attached. The high concentration part of the base region extends down to and protrudes into the high concentration buried region, resulting in a higher than usual collector-base capacitance. The latter causes the voltage change due to .alpha.-rays to be less than it otherwise would be.
    Type: Grant
    Filed: April 7, 1982
    Date of Patent: October 29, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Tsutomu Akashi
  • Patent number: 4549151
    Abstract: A pulse width modulator circuit includes a first comparator comparing an input signal with a sawtooth wave signal, a second comparator comparing a reference voltage with the sawtooth wave signal, an AND circuit receiving the outputs from the first and second comparators, and a reference voltage generator having a series connection of first and second resistors, a reference voltage output terminal being connected to the connection point between the resistors and a capacitor connected in parallel with one of the resistors. It is preferable to connect a switch circuit so that the reference voltage output may be lowered by an electrical switching signal.
    Type: Grant
    Filed: July 26, 1982
    Date of Patent: October 22, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Takashi Kaneko
  • Patent number: 4546368
    Abstract: An input part of a charge transfer device includes first, second and third gate electrodes on a semiconductor substrate. The first gate electrode is located close to a charge injection region but far from a shift register part. The third gate electrode is located close to the shift register part but far from the charge injection region. The second gate electrode is located between the first and third gate electrodes, and comprises two partial electrodes which are formed in different forming steps. One of the partial electrodes which is far from the first gate electrode is preferably formed by the same forming step as the first gate electrode.
    Type: Grant
    Filed: September 16, 1982
    Date of Patent: October 8, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Kenzo Yamanari
  • Patent number: 4546446
    Abstract: In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the multiplicand and coefficient are multiplied by each other to produce a partial product. Partial products are produced for every three consecutive bits of the multiplier, and the obtained partial products are added to the sum of previously obtained partial products. After all the partial products are added together, the resultant sum is derived from the adder or from the feed-back path of the output from the adder.
    Type: Grant
    Filed: February 25, 1982
    Date of Patent: October 8, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Toshiaki Machida
  • Patent number: 4546467
    Abstract: A monitoring device for monitoring the status of communication units connected to a common transmission medium. The monitoring device sequentially addresses each communication unit and transmits to the addressed unit an inquiry frame which includes in addition to the destination address, a source address field and a control information field. The addressed communication unit, if operating responds with a reply frame including the destination address of the monitor, its address, and a status information field. The received status information is compared with a previously received status information from the addressed control unit, and a primary fault is indicated when the compared informations do not coincide. A secondary fault is indicated if no reply frame is received from an addressed communication unit within a predetermined time from the transmission of the inquiry frame.
    Type: Grant
    Filed: February 3, 1983
    Date of Patent: October 8, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Sumio Yamamoto
  • Patent number: 4544291
    Abstract: An inked ribbon cartridge has two sets of ribbon feed mechanisms, one for each core means around which the ribbon is wound, allowing the ribbon to travel back and forth so that the cartridge can be loaded upside down when the upper half of the ribbon has been used up thereby doubling the useful life of the cartridge. Two springs apply a predetermined force to two ratchet wheels which are connected to first and second core means for preventing an over-rotation of the core means. Each feed mechanism comprises a feed driven roller and a feed drive roller.
    Type: Grant
    Filed: March 13, 1981
    Date of Patent: October 1, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Muneyoshi Nagata, Hiroshi Kano
  • Patent number: 4542406
    Abstract: The horizontal sync signal contained in the video signal from a video apparatus sometimes undergoes phase jump, resulting in failure of multiplexing of audio and video signals based on the horizontal sync signal. A sync signal switching circuit is adapted to produce a modified sync signal by switching the sync signal to a local sync signal upon occurrence of the phase jump, thereby assuring the multiplexing of audio and video signals.
    Type: Grant
    Filed: December 7, 1982
    Date of Patent: September 17, 1985
    Assignees: Nippon Electric Co., Ltd., Nippon Telegraph & Telephone Public Corporation, Fujitsu Limited
    Inventors: Haruo Shimoyama, Toshio Ohshima, Shinobu Nomoto, Makoto Hiraoka, Toshio Hanabata
  • Patent number: 4542306
    Abstract: In a buffer circuit for producing two output signals of the opposite phases in response to an input signal comprising a pre-circuit producing two pre-output signals in accordance with the input signal and a reference voltage signal; and a main circuit including a latch circuit latching the pre-output signals, and a flip-flop circuit connected to receive the pre-output signals latched by the latch circuit for producing the output signals of the buffer circuit, there is provided a transfer gate circuit enabled by the pre-output signals and disabled by the output signals of the buffer circuit. According to this invention, different from the prior art circuit, it is not necessary to use any clock signal having a high level at the time of operation of the buffer circuit and to have strict time spacing, whereby the clock signal generator can be simplified and the buffer circuit can be miniaturized and its operating speed can be increased.
    Type: Grant
    Filed: February 2, 1983
    Date of Patent: September 17, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroaki Ikeda
  • Patent number: 4542531
    Abstract: In a radio transmitter/receiver comprising a transmitter, a superheterodyne receiver, and a local oscillator for supplying a local oscillation signal to the superheterodyne receiver, the intermediate frequency f.sub.if of the superheterodyne receiver is set to have a value expressed byf.sub.if =(2K-1).times.f.sub.ch /2where f.sub.ch represents a frequency spacing between radio frequencies assigned to a communication and K represents a natural number.
    Type: Grant
    Filed: March 15, 1983
    Date of Patent: September 17, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Yukio Fukumura
  • Patent number: 4541624
    Abstract: A system for feeding a flat article has a suction chamber; a suction belt for picking up one of a plurality of flat articles which are stacked in a vertically standing state. The suction belt moves along the front surface of the suction chamber. The flat articles are carried over a transport path by the suction belt. At an upstream position in the transport path, the intervals between the flat articles are detected. First and second motors drive the suction belt, varying the rotational motor speeds. A roller along the transport path contacts the transferred flat articles in accordance with the interval which is detected by the detecting member.
    Type: Grant
    Filed: March 23, 1983
    Date of Patent: September 17, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Tsutomu Sasage, Tomohisa Yoshida, Toshio Yoshida
  • Patent number: 4542484
    Abstract: A memory device which has highly stabilized read-out characteristics and is suitable to a highly integrated structure is disclosed.The memory device comprises a flip-flop having first and second enhancement type field effect transistors which are cross-connected at first and second junction points, and third and fourth depletion type field effect transistors connected between said flip-flop and a pair of first and second bit lines and having their gates connected to a common third junction point of said flip-flop.
    Type: Grant
    Filed: August 5, 1982
    Date of Patent: September 17, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroaki Ikeda
  • Patent number: 4539530
    Abstract: A transistorized microwave oscillator comprising a resonator 2 coupled to a transistor 4, 5 and a feedback capacitor 7' around the transistor which produces a fundamental oscillation frequency and harmonics thereof. The feedback capacitor is located within a cut-off waveguide 21 and couples oscillations into the waveguide which blocks the lower undesired frequencies.
    Type: Grant
    Filed: March 28, 1983
    Date of Patent: September 3, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Motoo Mizumura, Kenzo Wada
  • Patent number: 4538151
    Abstract: An electro-magnetic wave absorbing member comprises a mixture of short fibers of metal or alloy having a high electroconductivity, a length of from 0.1 mm to 50 mm and a length to diameter ratio of larger than 10, ferrite and a high molecular weight synthetic resin. In a modification a sheet of this material is used as a low input impedance layer and laminated with an electroconductive sheet and an impedance conversion layer. The member of this invention can increase electrical loss contributing to the absorption of electric magnetic wave, can stably control the absorption and can be used in many applications.
    Type: Grant
    Filed: March 25, 1983
    Date of Patent: August 27, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Kenichi Hatakeyama, Tetsuji Inui
  • Patent number: 4538077
    Abstract: A circuit utilizing Josephson junctions to perform high speed logic gate switching functions. Three "Y" connected resistors have Josephson junction devices at their non-connected ends. The resistances of the resistors, the critical currents of the Josephson junctions, and the amplitudes of input currents to two of the resistor-Josephson junction connections are selected so that, when the input currents are applied at the same time, the third Josephson junction is switched to the voltage state and both input currents are derived from the third Josephson junction-resistor connection as an input current. In another embodiment, the basic circuit has additional resistor-Josephson junction input arms, producing an M/N logic gate function. In another embodiment, the resistors are ".DELTA." connected. The resulting logic gates have wide operational margins, high speed switching capabilities and small size.
    Type: Grant
    Filed: September 8, 1982
    Date of Patent: August 27, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Junichi Sone
  • Patent number: 4536881
    Abstract: An easily testable integrated logic circuit utilizes a plurality of flip-flops to form a feedback shift register. In some embodiments, means are provided for selectively forming the flip-flops into a feedback shift register and for selectively supplying either the flip-flop contents or a random signal as partial inputs to the combinational logic circuit. In other embodiments, the feedback shift register is coupled to the AND logic array outputs of a combinational circuit which also includes and OR logic array.
    Type: Grant
    Filed: October 27, 1983
    Date of Patent: August 20, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Yoshihiro Kasuya
  • Patent number: RE31996
    Abstract: In a microwave tube of the type wherein an electron beam emitted by an electron gun is focused and caused to interact with an input high frequency wave at a high frequency circuit unit by magnetic flux generated by a periodic permanent magnet assembly, and the electron beam after the interaction is collected by a collector unit, the portion connected to the output unit of the high frequency circuit unit comprises a column-shaped waveguide member having an end surface comprising a portion of the wall of a cavity at the end of the high frequency circuit unit, the member being bored with a central aperture at the center axis to allow electron beam to pass from the electron gun to the collector unit. A waveguide for guiding the electromagnetic waves from the end surface to the output unit is also provided, and the end surface is shaped like a fan.
    Type: Grant
    Filed: September 29, 1982
    Date of Patent: October 1, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hisaaki Sato