Abstract: A modular data processing unit includes first through fourth memories and an arithmetic unit all connected in a recirculating pipeline mode. An interface unit couples an external bus to the pipeline bus at a point between the arithmetic unit and first memory, and the fourth memory provides outputs to either the arithmetic unit or the interface unit. Data, instructions and addresses are transferred to the first memory via the interface unit, which addresses the second memory for storing instructions. In accordance with the output of the second memory, data is stored in the third memory. The arithmetic unit operates on the data in accordance with the instructions, and the fourth memory acts as a buffer for temporarily storing data while awaiting transfer to the arithmetic unit or interface unit. The transfer of data to the arithmetic unit from the fourth memory in addition to the transfer of data between modules, is controlled in accordance with the available storage capacity in the fourth memory.

Abstract: For use in combination with a loudspeaker and at least one microphone, for example, by attendants in an auditorium, an echo cancelling circuit comprises a self-adaptive echo canceller responsive to a lower frequency component, such as below 1.7 kHz, of a receive-in signal for self-adatively cancelling a corresponding component of a reverberation signal included in a send-in signal during each interval during which an audio signal reaches the circuit from a remote party. For a higher frequency reverberation signal component, an echo suppressor or a voice switch may reduce a weaker one of two signals which are either the higher frequency send-in and receive-in signal components or a combination of a reverberation component cancelled signal with the higher frequency send-in signal component and the whole receive-in signal. Alternatively, a less expensive echo canceller non-adaptively cancels a part of the reverberation signal in response to the receive-in signal.

Abstract: In a pager receiver (12) of a paging system, a reception controller (21) is kept operable when a switch (22) is closed. A first transistor (31) energizes a receiver part (16, 17) at the beginning of a call code part of a received calling signal. If a calling code for that receiver is detected at a certain call time slot of the call code part, the first transistor keeps the energization until the end of that call code part and again energizes the receiver part during a message time slot corresponding to that call time slot in a message code part which next follows that call code part in the received calling signal. A second transistor (32) energizes a display part (26-28) a little before that message time slot. If a message code is detected at that message time slot, the second transistor keeps the energization to generate an alert tone and a visual display. As soon as a blank message pattern is detected at that message time slot, the second transistor suspends the energization.

Abstract: In an information processing apparatus of the type comprising a CPU, a memory device and input and output device, where a portion of the memory region storing a plurality of bytes as a unit of data to be stored overlaps a portion of the memory region to which the data are transferred, there are provided an address difference calculating circuit for calculating the difference of the addresses at the data transfer and data receiving sides, a comparator for comparing respective addresses, and a recurrent data pattern forming circuit for exchanging data between the memory region for storing the data and the memory region for receiving the data by a number corresponding to the difference of the addresses.

Abstract: A flexible disk device, in which a handle member is manually operated to move a holding asembly which either holds a flexible disk in an operating position or releases the disk, for removal. A cam selectively couples a pair of magnetic heads simultaneously to engage the disk and to hold them in position. The cam also decouples the heads from the disk. The cam may comprise first and second cam sections, which are reversibly rotatable on both sides of the disk when it is held in an operating position, respectively. In this event, it is preferred to make a head withdrawing assembly to forcibly rotate the cam to withdraw the heads from the coupled state whenever the handle member is actuated to release the disk. The head withdrawing assembly may comprise a protrusion attached to the cam and an arm attached to the handle member which do not engage each other to leave the cam freely and reversibly rotatable when the disk is held in position.

Abstract: A segmented digital transversal filter comprising a first transversal filter 4 that eliminates all frequency components from a signal sequence above half the subsampling frequency, a second transversal filter 11 that convolutes the output of the first filter with a decimated and energy compensated lower band of filter coefficients (HI.sub.1 '), a third transversal filter 22 that convolutes the output of the first filter and a decimated and energy-compensated upper band of filter coefficients (HI.sub.2 '), and a fourth transversal filter 32 that convolutes the original signal sequence and the central band of filter coefficients (HI.sub.3). Delays 21 and 31 are added so that the outputs of the second, third and fourth filters arrive concurrently at an adder 51, the sum being the output of the invention.

Abstract: A parallel comparison type A/D converter comprises a voltage divider having 2.sup.N divider junctions connected in series between a reference voltage terminal and a ground potential terminal, 2.sup.N comparators for receiving as reference voltages the outputs of the respective divider junctions, a position detection logic circuit for receiving the outputs of the comparators, an encoder for receiving the output of the position detection logic circuit, and a code converter for receiving the output of the first digital encoder. The encoder adopts the Gray code format, and the code converter converts the Gray code format into the binary code format.

Abstract: A method of epitaxying layers on a semiconductor substrate through apertures in an insulating layer formed on a substrate. The layers are grown from the substrate and extend on the insulating layer by reacting dichlorosilane, hydrogen chloride and a carrier gas flow in a chamber under reduced pressure. The layers are used for semiconductors device formation.

Abstract: An improved semiconductor device operable at a high-speed and with a low power consumption is disclosed. The device comprises a common impurity-doped region, a first insulated gate field effect transistor utilizing the common impurity-doped region as a drain thereof, a second insulated gate field effect transistor utilizing the common impurity-doped region as a drain thereof, control means for controlling switching operations of the first and second transistor at the same time and means for deriving an output signal from the common impurity-doped region.

Abstract: The frequency divider includes a first or prescaling counter which selects between first and second frequency division factors, in response to a first control signal, and then divides an input signal frequency responsive to the first control signal. A second and programmable counter frequency divides the output of the first or prescaling counter by a third frequency-division factor. A third and programmable counter frequency divides the output of the first counter by a fourth frequency-division factor which is smaller than the third frequency-division factor. A switching control circuit then converts the output of the third counter and supplies the converted signal to the first counter, as the first control signal. The digital frequency divider is suitable for use a part of a phase-locked loop frequency synthesizer.

Abstract: A liquid crystal display device comprising a liquid crystal composition filled between one pair of electrode substrates at least one of which is transparent, said liquid crystal composition containing one or more blue dye(s) represented by the following general formula: ##STR1## wherein one of X and Y is amino group and the other is hydroxyl group; and R is alkyl group, alkoxy group, alkylthio group, aryl group, aralkyl group, aryloxy group, arylthio group, aralkyloxy group, aralkylthio group, halogen atom, piperidino group, piperazino group, morpholino group, pyrrolidino group or a group ##STR2## in which R.sub.1 and R.sub.2 are hydrogen atom, alkyl group, aryl group or aralkyl group; provided that the alkyl chain and the aryl ring in substituents R, R.sub.1 and R.sub.2 may optionally be substituted.

Abstract: In a portable radio device comprising a housing (20), a printed wiring board (11) encased in the housing, and a machine screw (50) for fastening the board to the housing through a tapped and a via hole (17) and (25), the machine screw has head and threaded portions (51) and (52) and an insulating cap (55) of a cylindrical shape covering the head portion and having at least one groove. Preferably, a pair of the grooves (56, 57) are formed parallel to an axis of the machine screw. The head portion may be circular or polygonal in cross section and have at least one screw slot. At least one groove may be formed on an upper end surface of the insulating cap. Alternatively, the machine screw may wholly be made of an insulating material.

Abstract: A multi-input logic circuit which operates in a push-pull manner is composed of first and second logic sections. The first logic section is coupled between an output terminal and a reference voltage source and composed of a plurality of enhancement field effect transistors receiving a plurality of first input signals. The second logic section is coupled between the output terminal and a power source and composed of a plurality of depletion field effect transistors receiving a plurality of second input signals complementary to the first logic signals.

Abstract: A display processing apparatus which can simply and easily control the size and display screen location of character patterns. The invention is comprised of a memory for storing character data of a predetermined size, an addressing circuit for reading out predetermined character data from the memory, and a transfer circuit for transferring the read character to a display circuit. The addressing circuit includes a counter, an arithmetic circuit for calculating A=MX+B, where X is the counter output value, M is a multiplication factor, B is a predetermined number and A is an address to be provided to the memory for reading out character data. An output shift register passes the memory output to the display circuitry only when the counter value is within predetermined limits, and a control circuit controls the values of the limits as well as M and B.

Abstract: A sampling frequency converting apparatus converts an input digital television signal which is sampled at a first frequency into an output digital signal which is sampled at a second frequency. The apparatus comprises a memory, a write-address producer which operates in response to the first frequency, a read-address producer which operates in response to the second frequency, and an interpolation circuit. The speed of the converting operation is determined by the difference between the first and second frequencies.

Abstract: In a wired substrate, a conductive pattern is formed of an alloy of gold, a base matal, and a noble metal and is contiguous to an insulating layer of a mixture of oxides of the base and the noble metals. The alloy preferably includes the base and the noble metals to a total amount of 0.2 to 2 percent by weight. More preferably, the base metal is titanium, aluminium, or copper. The noble metal is palladium, ruthenium, rhodium, or nickel. The wired substrate is manufactured by forming a first layer of the base metal, a second layer of the noble metal, and a selectively formed gold layer successively on the substrate and by heat treating at least the first, the second, and the gold layers to convert the gold layer and those portions of the first and the second layers on which the gold layer is formed, to the conductive pattern and to concurrently convert other portions of the first and the second layers to the insulating layer. The first, the second, and the gold layers are preferably 0.025 to 0.4, 0.025 to 0.

Abstract: A buffer circuit, which supplies current to a capacitive load, has a first circuit for reducing the power supply charging current to the capacitive load during switching intervals. The first circuit includes a charge storage device precharged between inverter switching intervals to produce at least a portion of the load charging current during the switching intervals. A second circuit includes a switching element connected between the power supply and the capacitive load to electrically connect the power supply through the second circuit to the load at a selected time in the switching interval to supplement the charging current produced by the charge storage device.

Abstract: There is provided a CMOSIC device including: first and second regions of a semiconductor substrate of a first conductivity type, the first and second regions being surrounded and isolated by a field insulating film formed in and on a major surface of the semiconductor substrate; a first MOS transistor which is formed in the first region and which has a source and a drain of a second conductivity type; a third region which is formed in the second region and which has a low resistance; and epitaxial layer of the second conductivity which is grown on the third region and which has a high resistance; and a second MOS transistor which is formed in the epitaxial layer and which has source and drain of the first conductivity type. The width of the field insulating film can be reduced to about half of that of the conventional field insulating film, thus improving the packing density of the semiconductor device.

Abstract: First and second ferrules of an optical fiber connector assembly are provided with angled apertures proximate their contacting ends. The angled apertures have a common axis when the two ferrules are assembled together, and the single optical fibers within the apertures are ground together with the ferrule end surfaces so that they are flush therewith. Feedback light resulting from end reflection is reflected outwardly of the cable, i.e. leaked, owing to the angularity of the fiber end surface with respect to the axis thereof.

Abstract: An expanded memory field is obtained by forming a physical address for accessing a main memory unit according to the present invention. The physical address is developed following an address-mode provided in an instruction including an address field. When the address-mode is a "1", physical address is provided by (i) obtaining a base offset address from a base register which is given by a base register bank as determined by a first field of the address field, and (ii) adding the base address to a displacement number determined by a second field of the address to obtain an offset address, (iii) obtaining a segment base address from a segment base address register corresponding to a segment number register determined by the first field of the address, and (iv) adding together the segment base address and the offset address. A 24 bit physical address is obtained. When the address-mode is a "0", the address field constitutes the offset address and the above additions are carried out.