Patents Assigned to Nippon Precision Circuits
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Patent number: 6429695Abstract: A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O1 and I/O2 of a latch circuit 1 are connected to the drain terminals of MOS transistors M1 and M2 having the same characteristics. Input terminals IN1 and IN2 are provided to the gate and source terminals of the MOS transistor M2, and input terminals IN3 and IN4 are provided to the gate and source terminals of the MOS transistor M2. A bias circuit 2 brings the MOS transistors M1 and M2 into the same bias state. The difference of the input signals supplied to the input terminals IN1 and IN2 is compared with the difference of the input signals supplied to the input terminals IN3 and IN4. Since the comparison result is outputted from the first and second input/output terminals I/O1 and I/O2, the input offset voltage does not affect the differential comparison circuit.Type: GrantFiled: November 6, 2001Date of Patent: August 6, 2002Assignees: Nippon Precision Circuits Inc., Yasuhiro SugimotoInventors: Satoru Miyabe, Yasuhiro Sugimoto
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Patent number: 6411172Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations, an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with.Type: GrantFiled: January 3, 2001Date of Patent: June 25, 2002Assignee: Nippon Precision Circuits, Inc.Inventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama
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Publication number: 20020070765Abstract: Automatic slice level control in response to differential input signals is enabled. Analog signals are transferred differentially to remove in-phase noise. Thus, its effects on S/N are alleviated. Ideal desired DSV (e.g., DSV=0) is accomplished. Also, the circuit scale is reduced, and the processing speed is enhanced. Analog differential input signals vinp and Vinn which are obtained by reading a recording medium and are inverted with respect to each other are supplied to input terminals in1 and in2 of a comparator (1) via resistors R1 and R2. A data stream is recorded on the recording medium while giving DSV=0. A charge pump (2) is driven by the digital signal from the comparator (1). A transconductance amplifier produces output currents Itrc1 and Itrc2 that are mutually differential signals and in proportion to the voltage difference between the output voltage Vcp from the charge pump (2) and a reference voltage Vref.Type: ApplicationFiled: October 11, 2001Publication date: June 13, 2002Applicant: Nippon Precision Circuits Inc.Inventor: Toshiaki Tsujikawa
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Patent number: 6380690Abstract: In a capacitive load drive circuit, in order to bring an output terminal used for supplying a drive voltage to a non-selected capacitive load into a high impedance state and in order to prevent the capacitive load from being unnecessarily driven by electric charge flowing to parasitic diodes at the output terminal, such as to prevent a non-selected electroluminescence element from turning on, a synchronizing unit generates second selecting signals by synchronizing first selecting signals to a clock signal constituting a basis of a drive signal of a common inverter for generating drive voltage to a common output terminal of plural electroluminescence elements, a drive signal generating unit brings individual output terminals into the high impedance state based thereon and a timing thereof is synchronized to a timing at which a potential difference between two poles of the non-selected electroluminescence element is nullified.Type: GrantFiled: June 8, 2001Date of Patent: April 30, 2002Assignee: Nippon Precision Circuits Inc.Inventor: Yoshiaki Inada
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Patent number: 6369731Abstract: The problem of the present invention is, in a plural-number order delta sigma D/A converter, not to cause click noise upon performing mute operation at no-signal input idling and hence to eliminate the necessity of a circuit for removing this. In order to perform sequence operation for rendering zero an output signal by lowering the order of a loop filter in order when stopping the operation of a plural-number order delta sigma D/A converter, 1st-order differentiators corresponding to each order and switch means for rendering inputs to these 1st-order differentiators zero are provided in the loop filter.Type: GrantFiled: November 28, 2000Date of Patent: April 9, 2002Assignee: Nippon Precision Circuits Inc.Inventors: Minoru Takeda, Yoshihiro Hanada, Akira Toyama
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Patent number: 6360349Abstract: A syndrome computing apparatus includes first syndrome computing circuit 2, 4 for receiving a predetermined number of bits of data (codewords) encoded based on a predetermined generator polynomial and performing a syndrome computation on the data inputted based on the generator polynomial. Shift register 1 delays the data by the predetermined number of bits. Second syndrome computing circuit 3, 5 receives the data delayed by the predetermined number of bits, and performs a syndrome computation on the data inputted based on the generator polynomial. Operating circuit 7, 8 vector-adds modulo 2 a first syndrome outputted by said first syndrome computing means to a second syndrome outputted by said second syndrome computing means. Outputs of said operating means 6, 7 are offered as a syndrome based on the generator polynomial.Type: GrantFiled: May 22, 1998Date of Patent: March 19, 2002Assignee: Nippon Precision Circuits, Inc.Inventor: Hiroyuki Kawanishi
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Patent number: 6351149Abstract: There is disclosed a MOS transistor output circuit capable of suppressing ringing and other noises and of operating at high speed under low power supply voltages. A signal corresponding to an input signal is applied to the gates of a first p-channel MOS transistor and a first n-channel MOS transistor. A control circuit detects the falling edge of the input signal to create a first signal. A second p-channel MOS transistor is held in conduction by the first signal during a period beginning with the rising edge of the output signal and ending with the instant at which the output signal can be regarded as having logic high (H) level. The rising edge of the input signal is detected to create a second signal. A second n-channel MOS transistor is held in conduction by the second signal during a period beginning with the falling edge of the output signal and ending with the instant at which the output signal can be regarded as having logic low (L) level.Type: GrantFiled: December 3, 1999Date of Patent: February 26, 2002Assignee: Nippon Precision Circuits, Inc.Inventor: Satoru Miyabe
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Patent number: 6346862Abstract: In a quartz oscillation circuit, electric current flowing through a quartz oscillator is reduced. Resistors Rg and Rd are provided respectively in any of paths formed by an output terminal, a capacitance element Cd and a power supply terminal VDD of a CMOS inverter 2 and any of paths formed by an input terminal, a capacitance element Cg and a power supply terminal VDD, thereby reducing a current flowing through a quartz oscillator. In particular, the total value of the resistors Rd and Rg is determined in a range of from 10&OHgr; to 320&OHgr;, thereby reducing a quartz current and obtaining a required negative resistance.Type: GrantFiled: March 5, 1999Date of Patent: February 12, 2002Assignee: Nippon Precision Circuits, Inc.Inventors: Eiichi Hasegawa, Haruhiko Otsuka
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Patent number: 6344812Abstract: An improved delta sigma digital-to-analog converter in which the thermometer code, which is output from a thermometer code converter, is divided into P blocks for every Q bits. An arrangement of the blocks is shifted in rotation by a barrel shifter at a frequency fs. Along with this, an arrangement of bits within each block is shifted in rotation by a shift register at a frequency of Q times fs. The bits within the code thus obtained are provided to local DACs, each specified to correspond to each of the given bits. In this manner, it is possible to maintain a lower operating frequency while at the same time to reducing the distortion in the output caused by a change in shifting the data in rotation in the local DACs, which change occurs depending on bit levels of the data in a form of the thermometer code.Type: GrantFiled: June 6, 2000Date of Patent: February 5, 2002Assignee: Nippon Precision Circuits, Inc.Inventors: Minoru Takeda, Yoshihiro Hanada
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Patent number: 6331724Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.Type: GrantFiled: December 23, 1997Date of Patent: December 18, 2001Assignee: Nippon Precision Circuits, Inc.Inventors: James T. Chen, Atsuo Yagi
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Patent number: 6329884Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inveter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption.Type: GrantFiled: October 8, 1998Date of Patent: December 11, 2001Assignee: Nippon Precision Circuits, Inc.Inventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama
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Patent number: 6292124Abstract: A delta-sigma D/A converter has a quantizer, a thermometer code converter portion, and an odd/even bit-interchanging portion. The quantizer produces a first digital signal. The thermometer code converter portion and odd/even bit-interchanging portion divide the output level of the first digital signal such that it is represented by the sum of the output levels of second and third digital signals. Each of the second and third digital signals has an output level obtained by dividing the output level of the first digital signal by a factor of 2 or an integer close to it. During the former half of each sampling interval, first and second adders produce, respectively, a level signal corresponding to the second digital signal and an inverted level signal corresponding to an inversion of the third digital signal.Type: GrantFiled: February 4, 2000Date of Patent: September 18, 2001Assignee: Nippon Precision Circuits, Inc.Inventors: Yoshihiro Hanada, Akira Toyama
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Patent number: 6242980Abstract: The first amplifier circuit D1 is formed by connecting drains of a pair of N-channel MOS transistors forming the first current mirror circuit CM1 respectively to the drains of P-channel MOS transistors 1 and 2 as a differential input portion, and the second amplifier circuit D2 is formed by connecting drains of a pair of P-channel MOS transistors forming the second current mirror circuit CM2 respectively to the drains of N-channel MOS transistors 5 and 6 as a differential amplifier circuit. The first and second differential amplifier circuits D1 and D2 can amplify the first and second signals having cycles corresponding with each other with their duty ratios kept unchanged regardless of their operating point potentials. Further, the two outputs are combined into one output to suppress variation of the operating point potential of the output attributable to process-related factors, fluctuation of the power supply potential due to the oscillating operation and the like.Type: GrantFiled: November 18, 1998Date of Patent: June 5, 2001Assignee: Nippon Precision CircuitsInventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama
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Patent number: 6218878Abstract: There is provided a D-type flip-flop circuit which is improved in terms of operating frequency. First and second current supplying circuits are provided as sources for supplying currents to first and third differential circuits for inputting data and to second and fourth differential circuits for holding data in a master circuit and a slave circuit. Further, timing for supplying the currents to the respective differential circuits for inputting and holding data are controlled by first and second clock signals, respectively. The D-type flip-flop circuit is improved in terms of operating frequency by optimizing timing for writing input data and timing for holding data by arranging the first clock signal so as to have a certain delay with respect to the second clock signal. Further, the D-type flip-flop circuit is improved with respect to the operating frequency also by optimizing the value of the currents supplied to the respective differential circuits.Type: GrantFiled: April 16, 1998Date of Patent: April 17, 2001Assignee: Nippon Precision Circuits, Inc.Inventor: Naoki Ueno
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Patent number: 6215370Abstract: A crystal oscillator circuit includes a CMOS invertor having an input terminal and an output terminal, a crystal resonator connected between the input terminal and the output terminal respectively at a first connection node and a second connection node, and a feedback resistor connected between the input terminal and the output terminal of the CMOS invertor. A first capacitor is provided between the first connection node and a power source terminal at a predetermined potential and a second capacitor is provided between the second connection node and a power source terminal at the predetermined potential. At least one resistor is disposed in series with at least one of the first capacitor and the second capacitor and has a resistance so as to limit a crystal current in the crystal resonator while maintaining negative resistance for stable oscillation. In an embodiment, a resistor is provided in series with each capacitor.Type: GrantFiled: January 8, 1998Date of Patent: April 10, 2001Assignee: Nippon Precision Circuits Inc.Inventors: Eiichi Hasegawa, Haruhiko Otsuka
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Patent number: 6191661Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with.Type: GrantFiled: December 21, 1998Date of Patent: February 20, 2001Assignee: Nippon Precision Circuits, Inc.Inventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama
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Patent number: 6171915Abstract: To provide a method of fabricating a MOS-type transistor of a LDD structure with a gate electrode made of molybdenum, which brings about a reduction in the amount of overlapping between the gate electrode and source/drain, a gate electrode is made of molybdenum and forms a first pattern. The first pattern is subject to nitriding process to form a second pattern. The second pattern includes an interior electrode layer and a nitride layer located outside of the electrode layer. The thickness of the nitride layer corresponds to the amount of overlapping between the second pattern and source/drain.Type: GrantFiled: June 11, 1996Date of Patent: January 9, 2001Assignee: Nippon Precision Circuits Inc.Inventor: Kuniyuki Hishinuma
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Patent number: 6157268Abstract: Increase of frequency and reduction of power consumption are advanced for a voltage controlled oscillation circuit. A capacitor C1 is connected between emitters of first and second transistors Tr1, Tr2 to receive an electric current from constant current sources Cs1, Cs2. Also, emitters of third and fourth transistors Tr3, Tr4 receive an electric current from a constant current source Cs3 and have their respective collectors connected through third and fourth resistors R3, R4 to a power supply terminal VCC. The respective collectors and bases of the third and fourth transistors Tr3, Tr4 are connected to bases and collectors of the first and second transistors Tr1, Tr2. Due to this, oscillation outputs are caused at respective ends of the capacitor C1, which has a voltage amplitude equal to a voltage drop due to the third and fourth resistors R3, R4 and values of currents flowing through them. The voltage drop can be decreased to such an extent that the first and second transistors Tr1, Tr2 can be turned on.Type: GrantFiled: January 19, 1999Date of Patent: December 5, 2000Assignee: Nippon Precision Circuits, IncInventor: Naoki Ueno
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Patent number: 6137365Abstract: There is disclosed a variable-gain circuit forming resistors on a semiconductor substrate. The ratio of the total resistance to the minimum resistance is made smaller than heretofore. The circuit is miniaturized. The variable-gain circuit comprises an operational amplifier, a first set of resistors R1-Rn+1, a second set of resistors Rx1-Rxm, switches SW1-SWn and a control circuit. This control circuit closes only one of the switches SW1-SWn at all times.Type: GrantFiled: August 20, 1998Date of Patent: October 24, 2000Assignee: Nippon Precision Circuits, Inc.Inventors: Hiroyuki Wakairo, Kazuyuki Fujiwara
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Patent number: 6101077Abstract: An electrostatic protection circuit of a semiconductor device comprises a first MOS transistor of specific conductive type and a second MOS transistor of the specific conductive type. In the first MOS transistor, a drain thereof is connected to an output terminal or an input terminal and a source thereof is connected to a first power terminal and the first MOS transistor is controlled to be on/off by a signal received by a gate or ordinarily turned off by holding the gate at a specific potential. In the second MOS transistor of the specific conductive type, a drain thereof is connected to the output terminal or the input terminal and a source thereof is connected to a gate of the first MOS transistor and the second MOS transistor is ordinarily turned off by connecting a gate thereof to the first power terminal.Type: GrantFiled: August 3, 1998Date of Patent: August 8, 2000Assignee: Nippon Precision Circuits Inc.Inventors: Toru Matsumoto, Yasuaki Otaka, Takashi Sumiya