Patents Assigned to Nippon Precision Circuits
  • Patent number: 5041897
    Abstract: A semiconductor device has a fuse element formed on an insulating substrate, and a first insulating layer formed on the substrate and covering the fuse element. Further insulation on the first insulating layer nitride has an opening exposing the region of the first insulating layer above said fuse.
    Type: Grant
    Filed: October 17, 1990
    Date of Patent: August 20, 1991
    Assignees: Seikosha Co., Ltd., Nippon Precision Circuits Ltd.
    Inventors: Koji Machida, Hideyuki Nakamura, Hiroshi Tonegi
  • Patent number: 5021850
    Abstract: A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film
    Type: Grant
    Filed: July 10, 1989
    Date of Patent: June 4, 1991
    Assignees: Seikosha Co., Ltd., Nippon Precision Circuits Ltd.
    Inventors: Sakae Tanaka, Yoshiaki Watanabe, Katsuo Shirai, Yoshihisa Ogiwara
  • Patent number: 5005056
    Abstract: A reverse staggered amorphous-silicon thin film transistor array substrate includes amorphous silicon thin film transistors in an array, gate wirings interconnecting the gate electrodes of the transistors, and source wirings of a transparent conductive layer connecting the source electrodes. An auxiliary source wiring of the material of the source electrodes of said transistors is provided under the source wiring.
    Type: Grant
    Filed: February 3, 1989
    Date of Patent: April 2, 1991
    Assignees: Nippon Precision Circuits Ltd., Seikosha Co., Ltd.
    Inventors: Noboru Motai, Sakae Tanaka, Yoshiaki Watanabe
  • Patent number: 4979006
    Abstract: A reverse staggered type silicon thin film transistor includes a substrate having a gate electrode; a gate insulating layer on the substrate and the gate electrode, the gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, the lower layer silicon film being formed at a first temperature and with a first thickness; an upper layer silicon film formed on the transistor-forming portion of the gate insulating layer at a second temperature which is lower than the first temperature and with a second thickness greater than the first thickness; and n-type silicon layer on the upper layer silicon film and in contact therewith; a source electrode on the n-type silicon layer; and a drain electrode on the n-type silicon layer.
    Type: Grant
    Filed: May 26, 1989
    Date of Patent: December 18, 1990
    Assignees: Seikosha Co., Ltd., Nippon Precision Circuits Ltd.
    Inventors: Sakae Tanaka, Yoshiaki Watanabe, Katsuo Shirai, Yoshihisa Ogiwara
  • Patent number: 4929947
    Abstract: A digital-to-analog converter comprising: a distributing circuit (2, 3, 4, 5; 2, 13, 14-26) for distributing data pulses, which are bit-serially supplied at constant time intervals, into a plurality of routesand for providing them as pulses having a constant width; and a converting circuit (12) for adding together the pulses from the distributing circuit and thereby for converting them to an analog output. Such a circuit arrangement can provide pulses for conversion to analog form which all have an identical waveform and an identical area, and errors caused by the difference between the rise and fall times of the pulses can be eliminated and therefore D/A conversion characteristics can be improved.
    Type: Grant
    Filed: April 4, 1988
    Date of Patent: May 29, 1990
    Assignee: Nippon Precision Circuits Ltd.
    Inventor: Akira Toyama
  • Patent number: 4916090
    Abstract: A method for manufacturing a amorphous silicon thin film transistor comprises exposing an morphous silicon layer situated between a source electrode and a drain electrode to a gas phase atmosphere having a gas containing an impurity forming an acceptor, then activating said impurity with an electric field or light energy and doping the activated impurity into said amorphous silicon layer. The gas may be a hydrogen compound and it may include an oxidizing gas.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: April 10, 1990
    Assignees: Nippon Precision Circuits Ltd., Seikosha Co., Ltd.
    Inventors: Noboru Motai, Yoshihisa Ogiwara, Yasunari Kanda
  • Patent number: 4892613
    Abstract: A light shielding thin film is provided on a light transmitting substrate, and the film is covered by a photoresist. The photoresist is exposed and developed to form a pattern, and the film is etched using the pattern as a mask. The pattern is then exposed through the substrate, using the film as a mask, the pattern then being developed to form a pattern of reduced size. The film is then etched using the reduced size pattern as a mask.
    Type: Grant
    Filed: December 27, 1988
    Date of Patent: January 9, 1990
    Assignees: Nippon Precision Circuits Ltd., Seikosha Co., Ltd.
    Inventors: Noboru Motai, Sakae Tanaka, Yoshiaki Watanabe, Katsuo Shirai, Yaeko Suzuki, Yoshihisa Ogiwara, Kazunori Saito, Keiko Shibuki
  • Patent number: 4600959
    Abstract: A characteristic curve indicative of a correlation between the ratio of rotational periods of tape supply and takeup reels and a remaining time or elapsed time for a running tape is approximated by straight lines, and clock pulses having frequencies corresponding to the slopes of the straight lines are counted by counters to measure the remaining or elapsed time. With this arrangement, the remaining time or elapsed time for the tape can be measured simply by counting clock pulses with a series of counters, without resorting to a complex arithmetic circuit.
    Type: Grant
    Filed: February 28, 1983
    Date of Patent: July 15, 1986
    Assignee: Nippon Precision Circuits Ltd.
    Inventor: Shinichi Akita