Abstract: Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal.

Abstract: A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.

Abstract: An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

Abstract: A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle.

Abstract: A radio apparatus correlates signal data with stored synchronization data to determine correlation data. The signal data represents a received radio-frequency signal that encodes a data frame, which has a synchronization preamble with a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The radio apparatus identifies a set of peaks in the correlation data, and uses a timing criterion to identify a plurality of subsets of the set of peaks, such that time values of the peaks of each identified subset satisfy the timing criterion. The radio apparatus calculates a correlation score Cj for each of the identified subsets from correlation values of the subset's peaks, and uses the correlation scores Cj to select a subset from the plurality of subsets. Timing or frequency synchronization information for the radio apparatus is determined from the peaks of the selected subset.

Abstract: An electronic device comprises a module configured to transfer data bus transactions from a transaction source domain to a transaction target domain. A first interface receives the transaction from the source domain using a transaction source ID. A second interface sends the transaction to the target domain using a transaction target ID. A look-up table has a plurality of index values and stores the transaction source ID against one of the index values. Mapping logic determines whether the look-up table contains the transaction source ID stored against any of the index values. When the transaction source ID is already stored, the transaction target ID is set to that index value. Conversely, when the transaction source ID is not stored, an available index value is selected, the transaction source ID is stored against that available index value, and the transaction target ID is set to that available index value.

Abstract: A method of mediating a read transaction from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The method includes receiving first and second read transactions associated with a first and second transaction ID, separating each read transaction into a plurality of sub-transactions, which have the second bus width. The method further includes sending a sub-transaction of each plurality of sub-transactions to the transaction target domain and receiving first data associated with the first transaction ID and second data associated with the second transaction ID, storing the first data in a first storage element assigned to a first list, storing the second data in a second storage element assigned to a second list; and reading out data to the transaction source domain from the first list and the second list independently of each other.

Abstract: A radio apparatus is configured to correlate signal data with stored synchronization data to generate synchronization correlation data. The signal data represents a received radio-frequency signal that encodes a data frame having a synchronization preamble comprising a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The synchronization correlation data is generated by correlating signal data representing the synchronization preamble with the stored synchronization data. While generating the synchronization correlation data, the radio apparatus identifies a first set of one or more peaks in the synchronization correlation data, and determines first synchronization information from the first set of one or more peaks.

Abstract: An integrated-circuit device comprises a physical-unclonable-function (PUF) unit, a secure module, and an interconnect system communicatively coupled to the PUF unit and to the secure module. The device transfers a PUF key from the PUF unit to the secure module, over the interconnect system. In order to do this, the secure module generates a random value. The secure module then sends the random value to the PUF unit. The PUF unit then performs a bitwise XOR operation between the received random value and the PUF key, to generate a masked value. The PUF unit then transfers the masked value over the interconnect system to the secure module. The secure module then unmasks the PUF key by performing a bitwise XOR operation between the received masked value and the random value.

Abstract: An electronic device comprises a bridge configured to transfer data bus transactions from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The bridge comprises a first interface configured to receive a transaction from the transaction source domain, where the transaction has a first transaction burst length. A converter logic is configured such that when a transaction is received via the first interface, the converter logic splits the transaction into a plurality of second transactions each having a respective second transaction burst length, wherein the plurality of second transactions have the second bus width. A second interface is configured to send the plurality of second transactions to the transaction target domain.

Abstract: A power supply circuit portion for supplying power comprises a first power rail, a second power rail, first and second output terminals, an energy storage device connected in parallel with the first and second output terminals; and first and second switching portions. The power supply circuit portion has a first mode in which power is supplied to the first and second output terminals by the first and second power rails, and a second mode in which the first switching portion is arranged such that power is not supplied to the first and second output terminals and the second switching portion is arranged to disconnect the energy storage device from the first power rail.

Abstract: An RF amplifier comprises a first ‘transconductance’ transistor (NCS) arranged to receive an RF input voltage (RFIN) at its gate terminal. A second ‘cascode’ transistor (NCG) has its source terminal connected to the drain terminal of the first transistor (NCS) at a node (MID). A feedback circuit portion is configured to measure a node voltage at the node (MID), to determine an average of the node voltage, to compare said average node voltage to a predetermined reference voltage (VBCG), and to generate a control voltage (CGGATE) dependent on the difference between the average node voltage and the predetermined reference voltage (VBCG). The feedback circuit portion applies the control voltage (CGGATE) to the gate terminal of the second transistor (NCG).

Abstract: An electronic device has an amplifier having an amplifier input terminal and an amplifier output terminal, the amplifier output terminal being connected to the device output terminal. An input capacitor is connected between the device input terminal and the amplifier input terminal. A feedback capacitor is connected between the amplifier output terminal and the amplifier input terminal. A switchable capacitor has a first terminal connected to the amplifier input terminal and a second terminal connected to a respective first terminal of each of a first switch and a second switch. The first switch has its second terminal connected to the device input terminal. The second switch has its second terminal connected to the amplifier output terminal. In this arrangement, the switchable capacitor can be switched between forming part of the input path of the amplifier or the feedback path of the amplifier.

Abstract: A method of operating an oscillator circuit comprising a resonator is provided. The method comprises maintaining a resonance of the resonator by a) connecting the resonator to an input voltage (Vbuf) for a first pulse period to charge the resonator only partially towards the input voltage (Vbuf); b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.

Abstract: A microcontroller comprises a processor and a memory. The memory comprises a first-stage bootloader, a first second-stage bootloader, a second second-stage bootloader region, and an application region for storing an application. The processor is configured to execute instructions from the first-stage bootloader when the microcontroller is reset. The first-stage bootloader comprises instructions for transferring execution from the first-stage bootloader to the active second-stage bootloader, which comprises instructions for transferring execution to an address in the application region, and for causing the processor to write a replacement second-stage bootloader to whichever of the first and second second-stage bootloader regions is not the active region.

Abstract: An integrated-circuit device comprising first and second radio systems. The first radio system comprises a first processor coupled to a first program memory and a first radio. The second radio system comprises a second processor coupled to a second program memory and a second radio. The device further comprises inter-processor communication (IPC) circuitry coupled to the first and second processors, for providing an IPC channel between the first and second processors. First software, stored in the first program memory for execution by the first processor comprises instructions for causing the first processor, in response to receiving a signal from the first radio, to send an electrical signal over the IPC channel to the second processor for causing second software stored in the second program memory to cause the second processor to send a command to the second radio.

Abstract: A handshake circuit portion for performing a handshake procedure to facilitate data reception by an associated circuit portion is provided. The handshake circuit portion comprises a request signal input for detecting a request signal from a further handshake circuit portion associated with a further circuit portion, an acknowledge signal output for asserting an acknowledge signal for the further handshake circuit portion, and a blocking signal input for detecting a blocking signal from the associated circuit portion. The handshake circuit portion is arranged to detect a request signal via the request signal input, determine if a blocking signal is present on the blocking signal input, and if a blocking signal is not present on the blocking signal input, respond to the request signal by asserting an acknowledge signal via the acknowledge signal output.

Abstract: A method of operating a radio receiver device comprises receiving a plurality of signals with a plurality of corresponding frequencies; applying respective gains to each of the plurality of signals; and storing the gain applied to each signal and its corresponding frequency. The method comprises subsequently receiving a further signal with a further frequency; and applying a further gain to the further signal. The further gain is determined using at least one of the stored gains according to a difference between the further frequency and at least one of the plurality of corresponding frequencies.