Patents Assigned to Novellus Systems, Inc.
  • Patent number: 10381266
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: August 13, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Tsung-Han Yang, Anand Chandrashekar, Jasmine Lin
  • Patent number: 10378109
    Abstract: A substrate processing system includes a processing chamber including a showerhead, a plasma power source and a pedestal spaced from the showerhead to support a substrate. A filter is connected between the showerhead and the pedestal. A variable bleed current circuit is connected between the filter and the pedestal to vary a bleed current. A controller is configured to adjust a value of the bleed current and configured to perform curve fitting based on the bleed current and DC self-bias voltage to estimate at least one of electrode area ratio, Bohm current, and radio frequency (RF) voltage at a powered electrode.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 13, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Edward Augustyniak, Douglas Keil
  • Patent number: 10351968
    Abstract: Apparatus and methods for electroplating are described. Apparatus described herein include anode supports including positioning mechanisms that maintain a consistent distance between the surface of the wafer and the surface of a consumable anode during plating. Greater uniformity control is achieved. The consumable anode in one implementation has a plurality of through channels and at least one depression on its surface (e.g., a depression surrounding a channel) that is configured for registering with a protrusion on a component of an anode assembly, such as with a support plate. Fasteners may pass through the channels in the anode and attach it to a charge plate.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: July 16, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Jingbin Feng, R. Marshall Stowell, Shantinath Ghongadi, Zhian He, Frederick Dean Wilmot
  • Patent number: 10325773
    Abstract: Disclosed are methods and systems for providing silicon carbide films. A layer of silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the silicon carbide film. The one or more radical species can be formed in a remote plasma source.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: June 18, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri N. Varadarajan, Bo Gong, Zhe Gui
  • Patent number: 10316409
    Abstract: A radical source for supplying radicals during atomic layer deposition semiconductor processing operations is provided. The radical source may include a remote volume, a baffle volume, and a baffle that partitions the remote volume from the baffle volume. The baffle volume and the remote volume may be fluidly connected through the baffle via a plurality of baffle holes. The baffle may be offset from a faceplate with a plurality of first gas distribution holes fluidly connected with the baffle volume. A baffle gas inlet may be fluidly connected with the baffle volume, and a first process gas inlet may be fluidly connected with the remote volume. Baffle gas may be flowed into the baffle volume to prevent radicalized first process gas in the remote volume from flowing through the baffle volume and the faceplate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 11, 2019
    Assignee: Novellus Systems, Inc.
    Inventor: Bart J. van Schravendijk
  • Patent number: 10309024
    Abstract: An apparatus for continuous simultaneous electroplating of two metals having substantially different standard electrodeposition potentials (e.g., for deposition of Sn—Ag alloys) comprises an anode chamber for containing an anolyte comprising ions of a first, less noble metal, (e.g., tin), but not of a second, more noble, metal (e.g., silver) and an active anode; a cathode chamber for containing catholyte including ions of a first metal (e.g., tin), ions of a second, more noble, metal (e.g., silver), and the substrate; a separation structure positioned between the anode chamber and the cathode chamber, where the separation structure substantially prevents transfer of more noble metal from catholyte to the anolyte; and fluidic features and an associated controller coupled to the apparatus and configured to perform continuous electroplating, while maintaining substantially constant concentrations of plating bath components for extended periods of use.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 4, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter
  • Patent number: 10301738
    Abstract: Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: May 28, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Bryan L. Buckalew, Steven T. Mayer, Thomas A. Ponnuswamy, Robert Rash, Brian Paul Blackman, Doug Higley
  • Patent number: 10283615
    Abstract: Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60° C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: May 7, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Dengliang Yang, Kwame Eason, Faisal Yaqoob, Joon Hong Park
  • Patent number: 10256142
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: April 9, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 10221484
    Abstract: A temperature controlled showerhead for chemical vapor deposition (CVD) chambers enhances heat dissipation to enable accurate temperature control with an electric heater. Heat dissipates by conduction through a showerhead stem and fluid passageway and radiation from a back plate. A temperature control system includes one or more temperature controlled showerheads in a CVD chamber with fluid passageways serially connected to a heat exchanger.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: March 5, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Henner W. Meinhold, Dan M. Doble, Stephen Yu-Hong Lau, Vince Wilson, Easwar Srinivasan
  • Patent number: 10224182
    Abstract: A system for reducing parasitic plasma in a semiconductor process comprises a first surface and a plurality of dielectric layers that are arranged between an electrode and the first surface. The first surface and the electrode have substantially different electrical potentials. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap and the third gap are selected to prevent parasitic plasma between the first surface and the electrode during the semiconductor process.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: March 5, 2019
    Assignee: NOVELLUS SYSTEMS, INC.
    Inventors: Douglas Keil, Edward Augustyniak, Karl Leeser, Mohamed Sabri
  • Patent number: 10214816
    Abstract: An apparatus for depositing film stacks in-situ (i.e., without a vacuum break or air exposure) are described. In one example, a plasma-enhanced chemical vapor deposition apparatus configured to deposit a plurality of film layers on a substrate without exposing the substrate to a vacuum break between film deposition phases, is provided. The apparatus includes a process chamber, a plasma source and a controller configured to control the plasma source to generate reactant radicals using a particular reactant gas mixture during the particular deposition phase, and sustain the plasma during a transition from the particular reactant gas mixture supplied during the particular deposition phase to a different reactant gas mixture supplied during a different deposition phase.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: February 26, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Jason Dirk Haverkamp, Pramod Subramonium, Joseph L. Womack, Dong Niu, Keith Fox, John B. Alexy, Patrick G. Breiling, Jennifer L. Petraglia, Mandyam A. Sriram, George Andrew Antonelli, Bart J. van Schravendijk
  • Patent number: 10214826
    Abstract: Certain embodiments herein relate to a method of electroplating copper into damascene features using a low copper concentration electrolyte having less than about 10 g/L copper ions and about 2-15 g/L acid. Using the low copper electrolyte produces a relatively high overpotential on the plating substrate surface, allowing for a slow plating process with few fill defects. The low copper electrolyte may have a relatively high cloud point.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: February 26, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Jian Zhou, Jon Reid
  • Patent number: 10211310
    Abstract: Provided are methods and systems for providing oxygen doped silicon carbide. A layer of oxygen doped silicon carbide can be provided under process conditions that employ silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the oxygen doped silicon carbide. The one or more radical species can be formed in a remote plasma source.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 19, 2019
    Assignee: NOVELLUS SYSTEMS, INC.
    Inventor: Bhadri Varadarajan
  • Patent number: 10192742
    Abstract: Methods for depositing nanolaminate protective layers over a core layer to enable deposition of high quality conformal films over the core layer for use in advanced multiple patterning schemes are provided. In certain embodiments, the methods involve depositing a thin silicon oxide or titanium oxide film using plasma-based atomic layer deposition techniques with a low high frequency radio frequency (HFRF) plasma power, followed by depositing a conformal titanium oxide film or spacer with a high HFRF plasma power.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: January 29, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Frank L. Pasquale, Shankar Swaminathan, Adrien LaVoie, Nader Shamma, Girish A. Dixit
  • Patent number: 10190230
    Abstract: The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. In many cases the material is a metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold defined on the bottom by the channeled plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through the channels in the channeled plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 29, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Richard Abraham, Steven T. Mayer, Bryan L. Buckalew, Robert Rash
  • Patent number: 10128102
    Abstract: Disclosed are pre-wetting apparatus designs and methods for cleaning solid contaminants from substrates prior to through resist deposition of metal. In some embodiments, a pre-wetting apparatus includes a process chamber having a substrate holder, and at least one nozzle located directly above the wafer substrate and configured to deliver pre-wetting liquid (e.g., degassed deionized water) onto the substrate at a grazing angle of between about 5 and 45 degrees. In some embodiments the nozzle is a fan nozzle configured to deliver the liquid to the center of the substrate, such that the liquid first impacts the substrate in the vicinity of the center and then flows over the center of the substrate. In some embodiments the substrate is rotated unidirectionally or bidirectionally during pre-wetting with multiple accelerations and decelerations, which facilitate removal of contaminants.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: November 13, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Lee Peng Chua, Bryan L. Buckalew, Thomas Anand Ponnuswamy, Brian Paul Blackman, Chad Michael Hosack, Steven T. Mayer
  • Patent number: 10121682
    Abstract: A purge ring for providing a gas to a wafer processing chamber includes an inlet ring wall defining a ring hole space. An outer perimeter of the inlet ring wall is elliptical. An outer perimeter of the ring hole space is circular. The inlet ring wall is a continuous structure surrounding the ring hole space. An inlet baffle formed within the inlet ring wall surrounds at least 180 degrees of the outer perimeter of the ring hole space. An inlet plenum arranged in a first end of the inlet ring wall provides the gas to the ring hole space through the inlet baffle. An exhaust channel is formed within the inlet ring wall in a second end of the inlet ring wall. An exhaust outlet hole arranged in the second end of the inlet ring wall exhausts the gas out of the ring hole space via the exhaust channel.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 6, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Eugene Smargiassi, Stephen Yu-Hong Lau, George D. Kamian, Ming Xi
  • Patent number: 10115608
    Abstract: A gas expansion module for use with semiconductor wafer loadlocks and other regulated-pressure components of semiconductor processing tools is provided. The gas expansion module may be barometrically isolated from the loadlock or other component and pumped down to a vacuum condition while the loadlock is performing operations at a higher pressure, such as ambient atmospheric conditions. After an initial pump-down of the loadlock is performed, the gas expansion module may be fluidly joined to the loadlock volume and the gases within each allowed to reach equilibrium. A further pump-down of the combined volume may be used to bring the loadlock pressure to a desired vacuum condition.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 30, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Edmund B. Minshall, Victor F. Morris, Ram Charan, Ronald A. Powell, Mukul Khosla
  • Patent number: 10106907
    Abstract: An apparatus for continuous simultaneous electroplating of two metals having substantially different standard electrodeposition potentials (e.g., for deposition of Sn—Ag alloys) comprises an anode chamber for containing an anolyte comprising ions of a first, less noble metal, (e.g., tin), but not of a second, more noble, metal (e.g., silver) and an active anode; a cathode chamber for containing catholyte including ions of a first metal (e.g., tin), ions of a second, more noble, metal (e.g., silver), and the substrate; a separation structure positioned between the anode chamber and the cathode chamber, where the separation structure substantially prevents transfer of more noble metal from catholyte to the anolyte; and fluidic features and an associated controller coupled to the apparatus and configured to perform continuous electroplating, while maintaining substantially constant concentrations of plating bath components for extended periods of use.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 23, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Lee Peng Chua, Steven T. Mayer, David W. Porter, Thomas A. Ponnuswamy