Abstract: A system for reducing parasitic plasma in a semiconductor process comprises a first surface and a plurality of dielectric layers that are arranged between an electrode and the first surface. The first surface and the electrode have substantially different electrical potentials. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap and the third gap are selected to prevent parasitic plasma between the first surface and the electrode during the semiconductor process.

Abstract: A temperature controlled showerhead for chemical vapor deposition (CVD) chambers enhances heat dissipation to enable accurate temperature control with an electric heater. Heat dissipates by conduction through a showerhead stem and fluid passageway and radiation from a back plate. A temperature control system includes one or more temperature controlled showerheads in a CVD chamber with fluid passageways serially connected to a heat exchanger.

Abstract: Certain embodiments herein relate to a method of electroplating copper into damascene features using a low copper concentration electrolyte having less than about 10 g/L copper ions and about 2-15 g/L acid. Using the low copper electrolyte produces a relatively high overpotential on the plating substrate surface, allowing for a slow plating process with few fill defects. The low copper electrolyte may have a relatively high cloud point.

Abstract: An apparatus for depositing film stacks in-situ (i.e., without a vacuum break or air exposure) are described. In one example, a plasma-enhanced chemical vapor deposition apparatus configured to deposit a plurality of film layers on a substrate without exposing the substrate to a vacuum break between film deposition phases, is provided. The apparatus includes a process chamber, a plasma source and a controller configured to control the plasma source to generate reactant radicals using a particular reactant gas mixture during the particular deposition phase, and sustain the plasma during a transition from the particular reactant gas mixture supplied during the particular deposition phase to a different reactant gas mixture supplied during a different deposition phase.

Abstract: Provided are methods and systems for providing oxygen doped silicon carbide. A layer of oxygen doped silicon carbide can be provided under process conditions that employ silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the oxygen doped silicon carbide. The one or more radical species can be formed in a remote plasma source.

Abstract: Methods for depositing nanolaminate protective layers over a core layer to enable deposition of high quality conformal films over the core layer for use in advanced multiple patterning schemes are provided. In certain embodiments, the methods involve depositing a thin silicon oxide or titanium oxide film using plasma-based atomic layer deposition techniques with a low high frequency radio frequency (HFRF) plasma power, followed by depositing a conformal titanium oxide film or spacer with a high HFRF plasma power.

Abstract: The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. In many cases the material is a metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold defined on the bottom by the channeled plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through the channels in the channeled plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.

Abstract: Disclosed are pre-wetting apparatus designs and methods for cleaning solid contaminants from substrates prior to through resist deposition of metal. In some embodiments, a pre-wetting apparatus includes a process chamber having a substrate holder, and at least one nozzle located directly above the wafer substrate and configured to deliver pre-wetting liquid (e.g., degassed deionized water) onto the substrate at a grazing angle of between about 5 and 45 degrees. In some embodiments the nozzle is a fan nozzle configured to deliver the liquid to the center of the substrate, such that the liquid first impacts the substrate in the vicinity of the center and then flows over the center of the substrate. In some embodiments the substrate is rotated unidirectionally or bidirectionally during pre-wetting with multiple accelerations and decelerations, which facilitate removal of contaminants.

Abstract: A purge ring for providing a gas to a wafer processing chamber includes an inlet ring wall defining a ring hole space. An outer perimeter of the inlet ring wall is elliptical. An outer perimeter of the ring hole space is circular. The inlet ring wall is a continuous structure surrounding the ring hole space. An inlet baffle formed within the inlet ring wall surrounds at least 180 degrees of the outer perimeter of the ring hole space. An inlet plenum arranged in a first end of the inlet ring wall provides the gas to the ring hole space through the inlet baffle. An exhaust channel is formed within the inlet ring wall in a second end of the inlet ring wall. An exhaust outlet hole arranged in the second end of the inlet ring wall exhausts the gas out of the ring hole space via the exhaust channel.

Abstract: A gas expansion module for use with semiconductor wafer loadlocks and other regulated-pressure components of semiconductor processing tools is provided. The gas expansion module may be barometrically isolated from the loadlock or other component and pumped down to a vacuum condition while the loadlock is performing operations at a higher pressure, such as ambient atmospheric conditions. After an initial pump-down of the loadlock is performed, the gas expansion module may be fluidly joined to the loadlock volume and the gases within each allowed to reach equilibrium. A further pump-down of the combined volume may be used to bring the loadlock pressure to a desired vacuum condition.

Abstract: An apparatus for continuous simultaneous electroplating of two metals having substantially different standard electrodeposition potentials (e.g., for deposition of Sn—Ag alloys) comprises an anode chamber for containing an anolyte comprising ions of a first, less noble metal, (e.g., tin), but not of a second, more noble, metal (e.g., silver) and an active anode; a cathode chamber for containing catholyte including ions of a first metal (e.g., tin), ions of a second, more noble, metal (e.g., silver), and the substrate; a separation structure positioned between the anode chamber and the cathode chamber, where the separation structure substantially prevents transfer of more noble metal from catholyte to the anolyte; and fluidic features and an associated controller coupled to the apparatus and configured to perform continuous electroplating, while maintaining substantially constant concentrations of plating bath components for extended periods of use.

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

Abstract: Disclosed herein are methods of cleaning a lipseal and/or cup bottom of an electroplating device by removing metal deposits accumulated in prior electroplating operations. The methods may include orienting a nozzle such that it is pointed substantially at the inner circular edge of the lipseal and/or cup bottom, and dispensing a stream of cleaning solution from the nozzle such that the stream contacts the inner circular edge of the lipseal and/or cup bottom while they are being rotated, removing metal deposits. In some embodiments, the stream has a velocity component against the rotational direction of the lipseal and/or cup bottom. In some embodiments, the deposits may include a tin/silver alloy. Also disclosed herein are cleaning apparatuses for mounting in electroplating devices and for removing electroplated metal deposits from their lipseals and/or cup bottoms. In some embodiments, the cleaning apparatuses may include a jet nozzle.

Abstract: Disclosed herein are cleaning discs for cleaning one or more elements of a semiconductor processing apparatus. In some embodiments, the disc may have a substantially circular upper surface, a substantially circular lower surface, a substantially circular edge joining the upper and lower surfaces, and a plurality of pores opening at the edge and having an interior extending into the interior of the disc. In some embodiments, the pores are dimensioned such that a cleaning agent may be retained in the interior of the pores by an adhesive force between the cleaning agent and the interior surface of the pores. Also disclosed herein are cleaning methods involving loading a cleaning agent into a plurality of pores of a cleaning disc, positioning the cleaning disc within a semiconductor processing apparatus, and releasing cleaning agent from the plurality of pores such that elements of the apparatus are contacted by the released cleaning agent.

Abstract: Disclosed herein are cups for engaging wafers during electroplating in clamshell assemblies and supplying electrical current to the wafers during electroplating. The cup can comprise an elastomeric seal disposed on the cup and configured to engage the wafer during electroplating, where upon engagement the elastomeric seal substantially excludes plating solution from a peripheral region of the wafer, and where the elastomeric seal and the cup are annular in shape, and comprise one or more contact elements for supplying electrical current to the wafer during electroplating, the one or more contact elements attached to and extending inwardly towards a center of the cup from a metal strip disposed over the elastomeric seal. A notch area of the cup can have a protrusion or an insulated portion on a portion of a bottom surface of the cup where the notch area is aligned with a notch in the wafer.

Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.

Abstract: Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.

Abstract: Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating.

Abstract: Porogen accumulation in a UV-cure chamber is reduced by removing outgassed porogen through a heated outlet while purge gas is flowed across a window through which a wafer is exposed to UV light. A purge ring having specific major and minor exhaust to inlet area ratios may be partially made of flame polished quartz to improve flow dynamics. The reduction in porogen accumulation allows more wafers to be processed between chamber cleans, thus improving throughput and cost.

Abstract: Methods of electroplating metal on a substrate while controlling azimuthal uniformity, include, in one aspect, providing the substrate to the electroplating apparatus configured for rotating the substrate during electroplating, and electroplating the metal on the substrate while rotating the substrate relative to a shield such that a selected portion of the substrate at a selected azimuthal position dwells in a shielded area for a different amount of time than a second portion of the substrate having the same average arc length and the same average radial position and residing at a different angular (azimuthal) position. For example, a semiconductor wafer substrate can be rotated during electroplating slower or faster, when the selected portion of the substrate passes through the shielded area.