Abstract: In one embodiment, an absorptive filter network is provided between an RF generator and a semiconductor processing reactor. The absorptive filter network includes an absorptive filter circuit which allows energies at a fundamental frequency to pass while absorbing energies at frequencies away from the fundamental frequency. An absorptive filter circuit is located on the reactor-side of the absorptive filter network to isolate the RF generator from the effects of the non-linear loading presented by a plasma in the reactor. Another absorptive filter circuit is located on the RF generator-side of the absorptive filter network to present a stable voltage waveform to the plasma.

Abstract: Ion-induced, UV-induced, and electron-induced sequential chemical vapor deposition (CVD) processes are disclosed where an ion flux, a flux of ultra-violet radiation, or an electron flux, respectively, is used to induce the chemical reaction in the process. The process for depositing a thin film on a substrate includes introducing a flow of a first reactant gas in vapor phase into a process chamber where the gas forms an adsorbed saturated layer on the substrate and exposing the substrate to a flux of ions, a flux of ultra-violet radiation, or a flux of electrons for inducing a chemical reaction of the adsorbed layer of the first reactant gas to form the thin film. A second reactant gas can be used to form a compound thin film. The ion-induced, UV-induced, and electron-induced sequential CVD process of the present invention can be repeated to form a thin film of the desired thickness.

Abstract: An apparatus and method for injecting gas within a plasma reactor and tailoring the distribution of an active species generated by the remote plasma source over the substrate or wafer. The distribution may be uniform, wafer-edge concentrated, or wafer-center concentrated. A contoured plate or profiler modifies the distribution. The profiler is an axially symmetric plate, having a narrow top end and a wider bottom end, shaped to redistribute the gas flow incident upon it. The method for tailoring the distribution of the active species over the substrate includes predetermining the profiler diameter and adjusting the profiler height over the substrate.

Abstract: A hollow cathode magnetron comprises an open top target within a hollow cathode. The open top target can be biased to a negative potential so as to form an electric field within the cathode to generate a plasma. The magnetron uses at least one electromagnetic coil to shape and maintain a density of the plasma within the cathode. The magnetron also has an anode located beneath the cathode. The open top target can have one of several different geometries including flat annular, conical and cylindrical, etc.

Abstract: The present invention pertains to systems and methods for simultaneously producing a diffusion barrier and a seed layer used in integrated circuit metallization. This is achieved by initially depositing copper-magnesium (Cu—Mg) alloys with relatively high levels of Mg (>10 atomic %, which is equivalent to about >4 weight %). After the alloys are deposited, they self-form a magnesium oxide (MgO) based barrier layer at the substrate interface, thus eliminating the need for a separate operation for barrier deposition. The migration of Mg to the substrate interface leaves the remainder of the film relatively pure Cu.

Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

Abstract: A vacuum valve assembly for use in a vacuum processing chamber includes a seat defining an opening in the vacuum valve, with the seat having a sealing face adjacent the opening and normal to the direction of the opening; and a gate having a sealing face adapted to mate with the seat sealing face, the gate being movable toward and away from the seat sealing face to seal and open the vacuum valve opening. A continuous elastomeric seal extends around the vacuum valve opening between the gate sealing face and the seat sealing face of sufficient size such that when the gate is positioned to seal the vacuum valve opening, there exists a gap between the gate sealing face and the seat sealing face. A purge gas port system, disposed in the seat or in the gate, has an inlet for a purge gas, an essentially continuous outlet extending around the vacuum valve opening and adjacent the elastomeric seal and gap, and a manifold system connecting the inlet and the outlet.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.

Abstract: A silicon carbon nitride (SiCN) layer is provided which has a low leakage current and is effective in preventing the migration or diffusion of metal or copper atoms through the SiCN layer. The SiCN layer can be used as a diffusion barrier between a metal portion (such as a copper line or via) and an insulating dielectric to prevent metal atom diffusion into the dielectric. The SiCN layer can also be used as an etchstop or passivation layer. The SiCN layer can be applied in a variety ways, including PECVD (e.g., using SiH4, CH4, and NH3) and HDP CVD (e.g.

Abstract: An apparatus for electroplating a wafer surface includes a cup having a central aperture defined by an inner perimeter, a compliant seal adjacent the inner perimeter, contacts adjacent the compliant seal and a cone attached to a rotatable spindle. The compliant seal forms a seal with the perimeter region of the wafer surface preventing plating solution from contaminating the wafer edge, wafer backside and the contacts. As a further measure to prevent contamination, the region behind the compliant seal is pressurized. By rotating the wafer during electroplating, bubble entrapment on the wafer surface is prevented. Further, the contacts can be arranged into banks of contacts and the resistivity between banks can be tested to detect poor electrical connections between the contacts and the wafer surface.

Abstract: The present invention pertains to methods for preventing metal or metal-derived material from flaking during sputter processing of substrates. Methods of the invention are particularly useful for non-planar sputter targets. The magnetic field configuration in a sputter apparatus is modulated during a pasting process. Flaking from regions of the target, shield, or other internal components of the sputter apparatus is inhibited by pasting methods which include encapsulation and optionally removal of material, for example by erosion via high density plasma.

Abstract: The present invention pertains to methods for forming metal-derived layers on substrates. Preferred methods apply to integrated circuit fabrication. In particular, selective methods may be used to form diffusion barriers on partially fabricated integrated circuits. In one preferred method, a wafer is heated and exposed to a metal vapor. Under specific conditions, the metal vapor reacts with dielectric surfaces to form a diffusion barrier, but does not react with metal surfaces. Thus, methods of the invention form diffusion barriers that selectively protect dielectric surfaces but leave metal surfaces free of diffusion barrier.

Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems apply liquid etchant in a precise manner at the edge bevel region of the wafer under viscous flow conditions, so that the etchant is applied on to the front edge area and flows over the side edge and onto the back edge in a viscous manner. The etchant thus does not flow or splatter onto the active circuit region of the wafer. An edge bevel removal embodiment involving that is particularly effective at obviating streaking, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.

Abstract: An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.

Abstract: A two-component porous material including small silicalite crystals in a porous binder provides a low dielectric constant material useful as an insulating layer in microelectronic devices. The silicalite/binder porous material uses silicalite nanocrystals smaller than the characteristic dimensions of the features on the integrated circuit device. The binder is an amorphous porous material that links the silicalite nanocrystals together, formed from a precursor which polymerizes on heating. The silicalite nanocrystals are supplied as a colloidal suspension or slurry. The slurry and binder precursor are spincoated onto a substrate and thermally treated to polymerize the binder precursor and drive off solvent in the slurry, forming the porous silicalite/binder material. The silicalite/binder porous material is readily integrated into standard damascene fabrication processes.

Abstract: The present invention pertains to systems and methods for improving the deposition of conformal copper seed layers in integrated circuit metalization. The invention involves controlling the morphology of the barrier layer deposited underneath the copper seed layer. The barrier layer can be composed of TaN and Ta, or TaN alone. It can also be composed of TiN or TiNSi. The process conditions of the barrier layer deposition are carried out in a manner that results in a highly or completely amorphous crystalline structure. Such a barrier layer allows for conformal deposition of the copper seed layer on top of the barrier layer that is less susceptible to agglomeration.

Abstract: Methods and an apparatus for providing a non-contact probe for accurately measuring the temperature of a substrate in a process chamber are disclosed. One exemplary apparatus is a processing chamber, which includes a heating source, where the heating source heats the substrate. Also included is a window maintained at a substantially constant temperature. The window allows only a first wavelength spectrum of energy emitted from the heating source to pass. In addition, the window isolates the heating source from an internal region of the processing chamber. A probe configured to detect a second wavelength spectrum of energy emitted directly from the substrate is included. The energy emitted directly from the substrate corresponds to a temperature of the substrate, and the temperature of the substrate is provided to the controller, which adjusts an intensity of the heating source based on a set point temperature for the substrate.

Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.

Abstract: Bowing of semiconductor wafers during heating is reduced by heating the wafers in a gas with a thermal conductivity and mean free path greater than that of oxygen, or by heating the wafers in a processing chamber under a pressure less than 0.1 Torr. In one embodiment, the high thermal conductivity gas is helium and heating in the helium takes place at a pressure less than 2.4 Torr.

Abstract: Each module of a wafer processing system is given a classification. Upon receipt of a command to move the wafer to one of the modules, a sequence enumerating the modules to be visited by the wafer before reaching its destination is created. The modules are added to the sequence based on their classification. The wafer is then worked on in each module enumerated in the sequence. By creating the sequence when needed, the number of static files that have to be maintained and stored in the wafer processing system is minimized. Further, creating the sequence at the time it is needed allows the sequence to take advantage of the history of the wafer and thereby eliminate unnecessary steps.