Patents Assigned to Novellus Systems
  • Patent number: 6797642
    Abstract: The present invention provides a method to improve adhesion of barrier, metal, dielectric interfaces. In the process flow, a first barrier material is formed on a dielectric layer and bombarded with a plasma to effectively push the barrier material into the dielectric interface while leaving a portion of the barrier material over the dielectric. A second barrier material, which may or may not be the same as the first barrier material, is then formed on the remaining first barrier material. Advantageously, the method of the present invention allows the barrier material to be pushed into the dielectric to insure excellent adhesion, which prevents chemical mechanical polishing delamination. Furthermore, the presence of the first barrier material on the sidewalls of via apertures through the dielectric can prevent Cu poisoning from sputtered Cu or CxOy.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: September 28, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Karen Chu, Anil Vijayendran, Michal Danek
  • Patent number: 6796314
    Abstract: Provided is a method for removing etch byproducts inside a contact hole while minimizing lateral etching of the contact hole. After an etching process, a wafer having a contact hole is placed inside a plasma reaction chamber. The contact hole contains etch byproducts that may degrade the quality of electrical connections. A radio frequency (RF) source creates a RF field inside the reaction chamber. A gas mixture containing chemicals that are reactive with the etch byproducts is introduced into the reaction chamber. The gas mixture becomes ionized by the RF field and reacts with the etch byproducts in the contact hole, removing the etch byproducts. The gas mixture may include approximately 10-60 vol. % hydrogen gas, a gas that reacts with the etch byproducts (e.g., NF3), and nitrogen. The hydrogen gas at least significantly reduces lateral etching of the contact hole by the reactive gas.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: September 28, 2004
    Assignee: Novellus Systems, Inc.
    Inventor: Wesley P. Graff
  • Publication number: 20040182424
    Abstract: An active rinse shield designed to protect electrofill chemical baths from excessive dilution during rinse sprays on the semiconductor wafer. The shield uses overlapping blades to cover the bath, making a physical barrier between the bath chemistry and the wafer rinse water. The blades are interconnecting ribs that actuate around a common pivot axis. A linear mechanical actuator controls the blade movement, moving the top-most blade, which in turn, moves an adjacent lower blade. Each upper blade is interconnected to an adjacent lower blade by upper and lower ledges, a pivot boss and interlocking cut, and a curved ledge on each blade's body surface. The interconnecting features allow the blades to move one another out for extension or in for retraction. The interlocking blades are inclined above one another, forming grooves to redirect the rinse water away from the chemical bath.
    Type: Application
    Filed: March 17, 2003
    Publication date: September 23, 2004
    Applicant: Novellus Systems, Inc.
    Inventors: Patrick Breiling, John D. Rasberry, Steve C. Schlegel
  • Patent number: 6794290
    Abstract: A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and hydrogen etch steps. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses a hydrogen-based plasma to chemically etch the deposited material to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: September 21, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: George D. Papasouliotis, Robert D. Tas
  • Patent number: 6793796
    Abstract: Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 21, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, David Smith, Steven T. Mayer, Jon Henri, Sesha Varadarajan
  • Patent number: 6790773
    Abstract: A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: September 14, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: John S. Drewery, Ronald A. Powell
  • Patent number: 6787483
    Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: September 7, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Atiye Bayman, Md Sazzadur Rahman, Weijie Zhang, Bart van Schravendijk, Vishal Gauri, George D. Papasoulitotis, Vikram Singh
  • Patent number: 6777349
    Abstract: Hermetic amorphous doped silicon carbide is deposited on an integrated circuit substrate in a PECVD reactor. Nitrogen-doping of an SiC film is conducted by flowing nitrogen-containing molecules, preferably nitrogen or ammonia gas, into the reactor chamber together with an organosilane, preferably tetramethylsilane, and forming a plasma. Oxygen-doping is conducted by flowing oxygen-containing molecules into the reaction chamber.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: August 17, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Haiying Fu, Ka Shun Wong, Xingyuan Tang, Judy Hsiu-Chih Huang, Bart Jan van Schravendijk
  • Patent number: 6778762
    Abstract: A processing chamber top is provided. The chamber top includes a top surface and a bottom surface having an inner and an outer edge. The bottom surface is sloped downward from the inner edge to the outer edge. A central opening extends through the chamber top. In one embodiment, the downward slope is between about 10 degrees and about 20 degrees. A method for processing a wafer in a processing chamber and a method for uniformly heating a substrate in a processing chamber are also provided.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: August 17, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Iqbal Shareef, Erez Shmuel, Syed Basha, Suwipin Martono
  • Patent number: 6773571
    Abstract: The present invention pertains to methods and apparatus for electroplating a substantially uniform layer of a metal onto a work piece having a seed layer thereon. The total current of a plating cell is distributed among a plurality of anodes in the plating cell in order to tailor the current distribution in the plating electrolyte to compensate for resistance and voltage variation across a work piece due to the seed layer. Focusing elements are used to create “virtual anodes” in proximity to the plating surface of the work piece to further control the current distribution in the electrolyte during plating.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: August 10, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Evan E. Patton, Brian Paul Blackman, Jonathan D. Reid, Thomas Anand Ponnuswamy, Harold D. Perry
  • Patent number: 6774039
    Abstract: Copper bus bars are formed between adjacent die on a wafer during the process flow. The bus bars are between 50 and 100 &mgr;m wide and between 2 and 5 &mgr;m deep. A barrier layer is formed between the bus bars and the die to prevent copper diffusion. A dielectric layer is deposited over the bus bars and die and etched with contacts and features, such as vias. A seed layer is subsequently deposited over the wafer, which allows electrical conductance between the bus bars and the die during a subsequent electroplating process to fill the features and contacts. The bus bars carry electroplating current from the die edge to the die center. As a result, current does not need to be carried by a low sheet resistivity seed layer from the wafer edge to the center. This allows the seed layer to be thinner and of materials other than copper. Further, thinner seed layers allow thicker barrier layer for more reliability.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Novellus Systems, Inc.
    Inventor: John S. Drewery
  • Patent number: 6766810
    Abstract: The present invention pertains to methods and apparatus for controlling the pressure in a supercritical processing system. Active methods for controlling the pressure include anticipating a pressure deviation due to a solute addition to a system, and changing the pressure within the system to compensate for the deviation. In this way, a desired pressure is achieved when the solute is added, without phase separation of the solute from the solvent. Pressure is adjusted by changing the volume of the supercritical processing system. Passive methods include adjusting the pressure of a supercritical system by changing the volume in response to a pressure deviation from a desired pressure. Apparatus for controlling the pressure in a supercritical processing system are described.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: July 27, 2004
    Assignee: Novellus Systems, Inc.
    Inventor: Patrick A. Van Cleemput
  • Patent number: 6767403
    Abstract: A spin bowl includes a base and a sidewall that extends from the base. The base has an upper portion for supporting a substrate in a horizontal plane and a lower portion that intersects with the sidewall. The lower portion of the base has a plurality of drain holes formed therein proximate to the sidewall. Each of the plurality of drain holes is configured to trap fluid therein during spinning of the spin bowl to thereby form a fluid seal that prevents air from flowing therethrough. In one embodiment, each of the drain holes is V-shaped. In another embodiment, the fluid seal is formed by the intersection of a straight drain hole with an external fluid catch area. An apparatus and method for spin coating a film over a substrate also are described.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: July 27, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Fred J. Chetcuti, Henner Meinhold
  • Publication number: 20040142557
    Abstract: Methods for depositing a tungsten nitride layer are described. The methods form a tungsten nitride layer using a carefully controlled deposition technique such as pulsed nucleation layer (PNL). Initially, a tungsten layer is formed on a substrate surface. The tungsten layer is then exposed to a nitriding agent to form a tungsten nitride layer. Methods of forming relatively thick layers of involve repeated cycles of contact with reducing agent, tungsten precursor and nitriding agent. In some cases, the cycle may also include contact with a dopant precursor such as phosphine or arsine.
    Type: Application
    Filed: October 20, 2003
    Publication date: July 22, 2004
    Applicant: Novellus Systems, Inc.
    Inventors: Karl B. Levy, Junghwan Sung, Kaihan A. Ashtiani, James A. Fair, Joshua Collins, Juwen Gao
  • Patent number: 6764552
    Abstract: Disclosed formulations of supercritical solutions are useful in wafer cleaning processes. Supercritical solutions of the invention may be categorized by their chemistry, for example, basic, acidic, oxidative, and fluoride chemistries are used. Such solutions may include supercritical carbon dioxide and at least one reagent dissolved therein to facilitate removal of waste material from wafers, particularly for removing photoresist and post-etch residues from low-k materials. This reagent may include an ammonium carbonate or bicarbonate, and combinations of such reagents. The solution may include one or more co-solvents, chelating agents, surfactants, and anti-corrosion agents as well.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: July 20, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Patrick C. Joyce, Adrianne Tipton, Krishnan Shrinivasan, Dennis W. Hess, Satyanarayana Myneni, Galit Levitin
  • Patent number: 6764952
    Abstract: Two sequential treatments within a chemical vapor deposition chamber, or within sequential chambers without a vacuum break, are performed on a copper layer to clean and passivate the copper surface prior to deposition of a copper diffusion barrier layer or a dielectric layer. The first treatment includes an ammonia, a hydrogen, or a hydrocarbon plasma cleaning of the copper surface followed by a short initiation of an organosilane precursor or a thin silicon nitride layer. A copper diffusion barrier layer may then be formed over the pretreated copper surface using an organosilane plasma, with or without a carbon dioxide or a carbon monoxide, or a silane with a nitrogen gas and an ammonia gas. Copper diffusion is retarded and film adhesion is improved for a dielectric layer or a copper diffusion barrier layer on the copper surface.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: July 20, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Jengyi Yu, Ka Shun Wong, Sanjeev Jain, Somnath Nag, Haiying Fu, Atul Gupta, Bart J. Van Schravendijk
  • Patent number: 6764168
    Abstract: In one embodiment, a sensor includes two plates that form a capacitor. A droplet passing between the plates changes the capacitance of the sensor, thereby triggering an amplifier coupled to the sensor to generate an output signal. The output signal is indicative of droplet characteristics and may be used to calibrate a mechanism that dispensed the droplet.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: July 20, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Henner W. Meinhold, Mark L. Rea, Sachin M. Chinchwadkar, Fred J. Chetcuti, John S. Drewery
  • Patent number: 6764940
    Abstract: Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: July 20, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Robert Rozbicki, Michal Danek
  • Publication number: 20040136681
    Abstract: An optical planar waveguide comprising erbium-doped silica glass has an active core with a length of not less than 5 cm, typically in a range of 0.2 cm to 100 meters, preferably 0.5 cm to 5 meters. Preferably, the active core of the planar waveguide has a serpentine shape. The radius of curvature of the serpentine planar waveguide is in a range of about 0.1 mm to 50 mm, preferably about 20 mm. The erbium-doped silica glass has a low concentration of erbium atoms, corresponding to an Er/Si atomic ratio in a range of 10−5 to 2×10−3, preferably in a range of about from 5×10−5 to 3×10−4. A layer of erbium-doped silica glass having a low concentration of erbium is formed on a substrate by sublimating a solid source of an erbium-containing metal organic precursor compound, mixing vaporized molecules of the precursor with other gases for forming silica glass, and: generating a plasma in the reaction mixture.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 15, 2004
    Applicant: Novellus Systems, Inc.
    Inventors: John S. Drewery, Douglas D. Cannon
  • Patent number: 6762849
    Abstract: A method and system for real-time, in-situ measurement of a film being deposited onto a surface of a wafer in a tool during semiconductor, optical component and electro-optic component processing and manufacturing. The method and system include real-time, in-situ detecting and analyzing radiation within the tool which is reflected off a wafer surface and subsequently diffusely reflected off internal roughened surfaces of the processing chamber. The emitted radiation may be derived from the plasma within the chamber, or alternatively, an external energy source. In detecting and analyzing the radiation reflected off the internal surfaces of the processing tool, the instant method and system monitors the deposition process of the film and automatically controls the deposition of such film in response to the measurements taken.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: July 13, 2004
    Assignee: Novellus Systems, Inc.
    Inventor: Ron Rulkens