Patents Assigned to Numerical Technologies
-
Patent number: 6811935Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. In one approach, phase shift regions are laid out so that they extend around corners in a feature, and in one or more identified corners having greater process latitude, the phase shift regions are divided and assigned opposite phases in the corner.Type: GrantFiled: September 5, 2002Date of Patent: November 2, 2004Assignee: Numerical Technologies, Inc.Inventor: Christophe Pierrat
-
Patent number: 6808850Abstract: One embodiment of the invention provides a system that performs optical proximity correction (OPC) on selected segments on a trim mask used in fabricating an integrated circuit. Upon receiving the trim mask, the system identifies selected segments on the trim mask that do not abut any feature to be printed on the integrated circuit. Next, the system performs a number of OPC operations. The system performs a first OPC operation on the selected segments to correct the selected segments. The system also performs a second OPC operation to correct segments on the trim mask that do abut features to be printed on the integrated circuit. The system additionally performs a third OPC operation on an associated phase shifting mask to correct segments that abut features to be printed on the integrated circuit. (Note that the first, second and third OPC operations can be performed separately or at the same time.Type: GrantFiled: October 21, 2002Date of Patent: October 26, 2004Assignee: Numerical Technologies, Inc.Inventor: Christophe Pierrat
-
Publication number: 20040209193Abstract: Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions, except for relative dosing. In another embodiment, the relative dosing between the phase and trim patterns is 1.0:r, 2.0<r<4.0. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.Type: ApplicationFiled: May 7, 2004Publication date: October 21, 2004Applicant: Numerical Technologies, Inc.Inventors: Christophe Pierrat, Michel Luc Cote
-
Publication number: 20040209176Abstract: Shifters on a phase shifting mask (PSM) can be intelligently assigned their corresponding phase. Specifically, the phase of a shifter can be assigned based on simulating the contrast provided by each phase for that shifter. The higher the contrast, the better the lithographic performance of the shifter. Therefore, the phase providing the higher contrast can be selected for that shifter. To facilitate this phase assignment, a pre-shifter can be placed relative to a feature on the layout. The pre-shifter can then be divided into a plurality of shifter tiles for contrast analysis. Model-based data conversion allows for a comprehensive solution including both phase assignment as well as optical proximity correction.Type: ApplicationFiled: May 12, 2004Publication date: October 21, 2004Applicant: Numerical Technologies, Inc.Inventor: Christophe Pierrat
-
Patent number: 6807663Abstract: Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a non-critical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this non-critical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.Type: GrantFiled: September 23, 2002Date of Patent: October 19, 2004Assignee: Numerical Technologies, Inc.Inventors: Michel Luc Côté, Christophe Pierrat, Philippe Hurat
-
Publication number: 20040202965Abstract: A photolithographic mask used for defining a layer in an integrated circuit, or other work piece, where the layer comprises a pattern including a plurality of features to be implemented with phase shifting in phase shift regions is laid out including for patterns comprising high density, small dimension features, and for “full shift” patterns. The method includes identifying cutting areas for phase shift regions based on characteristics of the pattern. Next, the process cuts the phase shift regions in selected ones of the cutting areas to define phase shift windows, and assigns phase values to the phase shift windows. The phase shift values assigned comprise &phgr; and &thgr;, so that destructive interference is caused in transitions between adjacent phase shift windows having respective phase shift values of &phgr; and &thgr;. In the preferred embodiment, &phgr; is equal to approximately &thgr;+180 degrees.Type: ApplicationFiled: April 29, 2004Publication date: October 14, 2004Applicant: Numerical Technologies, Inc.Inventors: Christophe Pierrat, Michel Luc Cote
-
Publication number: 20040197680Abstract: A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.Type: ApplicationFiled: May 12, 2004Publication date: October 7, 2004Applicant: Numerical Technologies, Inc.Inventors: Yao-Ting Wang, Yagyensh C. Pati
-
Publication number: 20040197672Abstract: Printing very small features on a wafer may require optimizing an illumination configuration in the lithographic imaging system. In a conventional system, an aperture provides only one illumination configuration. In contrast, a programmable aperture can ensure that each mask design is printed using its optimized illumination configuration while minimizing the amount of hardware in the system. The programmable aperture can include a grid of pixels, wherein each pixel can be controlled to provided a predetermined light state. Once installed, the programmable aperture can provide any number of illumination configurations, thereby eliminating the expense of fabricating, testing, and repairing multiple apertures as well as the time associated with installing those multiple apertures.Type: ApplicationFiled: April 1, 2003Publication date: October 7, 2004Applicant: Numerical Technologies, Inc.Inventors: J. Tracy Weed, Fang-Cheng Chang
-
Publication number: 20040191650Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.Type: ApplicationFiled: April 6, 2004Publication date: September 30, 2004Applicant: Numerical TechnologiesInventor: Christophe Pierrat
-
Patent number: 6797441Abstract: When substantially all of a layout for a layer of material in an integrated circuit (IC) is being defined using a phase shifting mask, the complementary mask used to define the remaining features and edges can be improved if some of the cuts on the complementary mask are substantially 180-degrees out of phase with one another. This helps cuts that are close to one another to print better and prevents undesirable deterioration of the features printed using the phase mask. Additionally, (semi-)isolated cuts can be reinforced with assist bars to ensure that the cut clears the unexposed regions left by phase conflicts.Type: GrantFiled: November 14, 2002Date of Patent: September 28, 2004Assignee: Numerical Technologies, Inc.Inventor: Christophe Pierrat
-
Publication number: 20040185351Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.Type: ApplicationFiled: March 26, 2004Publication date: September 23, 2004Applicant: Numerical Technologies, Inc.Inventors: Michel Luc Cote, Christophe Pierrat
-
Patent number: 6794096Abstract: Image intensity imbalance created by a phase shifting mask (PSM) layout can be corrected using a near-field image. Because an aerial image is not used, various parameters associated with the exposure conditions and stepper need not be considered, thereby significantly simplifying the computations to determine the appropriate correction. Of importance, using the near-field image can provide substantially the same correction generated using the aerial image. Thus, using the near-field image can provide an accurate and quick correction for image intensity imbalance between shifters of different phases. After correcting for the image intensity imbalance, additional proximity correction techniques can be applied to the layout to correct for other effects.Type: GrantFiled: October 9, 2002Date of Patent: September 21, 2004Assignee: Numerical Technologies, Inc.Inventor: Armen Kroyan
-
Patent number: 6795168Abstract: One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.Type: GrantFiled: April 8, 2002Date of Patent: September 21, 2004Assignee: Numerical Technologies, Inc.Inventors: Yao-Ting Wang, Christophe Pierrat, Fang-Cheng Chang
-
Patent number: 6795955Abstract: One embodiment of the invention provides a system for speeding up processing of a layout of an integrated circuit that has been divided into cells. The system operates by determining if a target cell in the layout is identical to a preceding cell for which there exists a previously calculated solution by comparing an identifier created from the target cell with an identifier created from the preceding cell. If the target cell is identical to a preceding cell, the system uses the previously calculated solution as a solution for the target cell. Otherwise, if the target cell is not identical to the preceding cell, the system processes the target cell to produce the solution for the target cell. Note that this approach can also be used for a number of different processes, such as distributed fracturing or optical proximity correction.Type: GrantFiled: March 15, 2002Date of Patent: September 21, 2004Assignee: Numerical TechnologiesInventors: Kevin D. MacLean, Roger W. Sturgeon
-
Patent number: 6792592Abstract: One embodiment of the invention provides a system that performs optical proximity correction in a manner that accounts for properties of a mask writer that generates a mask used in printing an integrated circuit. During operation, the system receives an input layout for the integrated circuit. The system also receives a set of mask writer properties that specify how the mask writer prints features. Next, the system performs an optical proximity correction process on the input layout to produce an output layout that includes a set of optical proximity corrections. This optical proximity correction process accounts for the set of mask writer properties in generating the set of optical proximity corrections, so that the mask writer can accurately produce the set of optical proximity corrections.Type: GrantFiled: August 30, 2002Date of Patent: September 14, 2004Assignee: Numerical Technologies, Inc.Inventors: Danny Keogan, Christophe Pierrat
-
Patent number: 6792590Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge.Type: GrantFiled: September 29, 2000Date of Patent: September 14, 2004Assignee: Numerical Technologies, Inc.Inventors: Christophe Pierrat, Youping Zhang
-
Publication number: 20040175634Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.Type: ApplicationFiled: March 12, 2004Publication date: September 9, 2004Applicant: Numerical Technologies, Inc.Inventors: Michel Luc Cote, Christophe Pierrat
-
Patent number: 6787271Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.Type: GrantFiled: February 28, 2002Date of Patent: September 7, 2004Assignee: Numerical Technologies, Inc.Inventors: Michel Luc Côté, Christophe Pierrat
-
Publication number: 20040172611Abstract: To exam mask defect impact during the transfer of a mask pattern to a wafer layer, tools can use mask images obtained during mask inspection. Specifically, these tools can also use optical models of such mask images to simulate wafer images. However, when feature sizes become very small, optical models may not provide sufficiently accurate simulation results. Using a photoresist model would yield significantly more accurate simulation results than using an optical model. Unfortunately, resist modeling is very slow, thereby making it commercially impractical. A simulation tool can generate a simulated wafer image having the accuracy of a photoresist model with the speed of an optical model by using a threshold look-up table. In one embodiment, the threshold look-up table could include variables such as feature size, pitch size, feature type, and defect type.Type: ApplicationFiled: February 23, 2004Publication date: September 2, 2004Applicant: Numerical Technologies, Inc.Inventor: Linyong Pang
-
Patent number: 6785879Abstract: Shifters on a phase shifting mask (PSM) can be intelligently assigned their corresponding phase. Specifically, the phase of a shifter can be assigned based on simulating the contrast provided by each phase for that shifter. The higher the contrast, the better the lithographic performance of the shifter. Therefore, the phase providing the higher contrast can be selected for that shifter. To facilitate this phase assignment, a pre-shifter can be placed relative to a feature on the layout. The pre-shifter can then be divided into a plurality of shifter tiles for contrast analysis. Model-based data conversion allows for a comprehensive solution including both phase assignment as well as optical proximity correction.Type: GrantFiled: June 11, 2002Date of Patent: August 31, 2004Assignee: Numerical Technologies, Inc.Inventor: Christophe Pierrat