Abstract: A mask fabrication and repair technique including multiple exposures is provided. In this multiple exposure technique, the first exposure can define the critical dimensions (CDs) of the shapes for the mask. A subsequent exposure can eliminate isolated defects and significantly reduce the size of defects proximate to the desired shapes on the mask. Because similar processes (i.e. forming, exposing, and developing a photoresist layer) are used for creating and repairing the mask, certain repair-related defects, such as phase and transmission defects, can be minimized. Wafer repair can also be performed using the same multiple exposure technique.

Abstract: When substantially all of a layout for a layer of material in an integrated circuit (IC) is being defined using a phase shifting mask, the complementary mask used to define the remaining features and edges can be improved if some of the cuts on the complementary mask are substantially 180-degrees out of phase with one another. This helps cuts that are close to one another to print better and prevents undesirable deterioration of the features printed using the phase mask. Additionally, (semi-)isolated cuts can be reinforced with assist bars to ensure that the cut clears the unexposed regions left by phase conflicts.

Abstract: An accurate, cost-effective system and method for correcting 3D effects on an alternating phase-shifting mask (PSM) is provided. To facilitate this correction, a library can be built to include a first group of 180 degree phase-shifting regions, wherein these regions have a common first size. Based on this first size, 3D simulation is performed. A transmission and a phase are altered in a 2D simulation based on this first size until a shape dependent transmission and a shape dependent phase allow the 2D simulation to substantially match the 3D simulation. Finally, a modified first size is chosen using the shape dependent transmission and the shape dependent phase such that a 2D simulation based on the modified first size substantially matches the 3D simulation based on the first size. The library associates the first size with the modified first size, the shape dependent transmission, and the shape dependent phase.

Abstract: One embodiment of the invention provides a system that performs optical proximity correction (OPC) on selected segments on a trim mask used in fabricating an integrated circuit. Upon receiving the trim mask, the system identifies selected segments on the trim mask that do not abut any feature to be printed on the integrated circuit. Next, the system performs a number of OPC operations. The system performs a first OPC operation on the selected segments to correct the selected segments. The system also performs a second OPC operation to correct segments on the trim mask that do abut features to be printed on the integrated circuit. The system additionally performs a third OPC operation on an associated phase shifting mask to correct segments that abut features to be printed on the integrated circuit. (Note that the first, second and third OPC operations can be performed separately or at the same time.

Abstract: Image intensity imbalance created by a phase shifting mask (PSM) layout can be corrected using a near-field image. Because an aerial image is not used, various parameters associated with the exposure conditions and stepper need not be considered, thereby significantly simplifying the computations to determine the appropriate correction. Of importance, using the near-field image can provide substantially the same correction generated using the aerial image. Thus, using the near-field image can provide an accurate and quick correction for image intensity imbalance between shifters of different phases. After correcting for the image intensity imbalance, additional proximity correction techniques can be applied to the layout to correct-for other effects.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: A method for producing a computer readable definition of photolithographic mask used to define a target pattern is provided. The phase shift mask patterns include phase shift windows, and the trim mask patterns include trim shapes, which have boundaries defined by such sets of line segments. For a particular pair of phase shift windows used to define a target feature in a target pattern, each of the phase shift windows in the pair can be considered to have a boundary that includes at least one line segment that abuts the target feature. Likewise, a complementary trim shape used in definition of the target feature, for example by including a transmissive region used to clear an unwanted phase transition between the particular pair of phase shift windows, includes at least one line segment that can be considered to abut the target feature.

Abstract: Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a noncritical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this noncritical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.

Abstract: Masks that include optical proximity correction or phase shifting regions are increasingly being used in the manufacturing process. These masks, either initially or after repair, can have “soft” defects, e.g. phase and/or transmission defects. In accordance with one feature of the invention, soft defect information can be computed from standard test images of a mask. This soft defect information can be used to generate an accurate simulated wafer image, thereby providing valuable defect impact information to a user. Knowing the impact of the soft defect can enable a user to make better decisions regarding the mask. Specifically, a user can now with confidence accept the mask for the desired lithographic process, repair the mask at certain critical locations, or reject the mask, all without exposing a wafer.

Abstract: One embodiment of the present invention provides a system that uses an exposure through a second mask to assist an exposure through a phase shifting mask in printing a tight space adjacent to a large feature. During operation, the system exposes a photoresist layer on the surface of a semiconductor wafer through the phase-shifting mask. This phase-shifting mask includes phase shifters that define a space between a first feature and a second feature, wherein the first feature is so large that the effectiveness of phase shifting is degraded in defining the space. Moreover, the degradation in phase shifting and the tightness of the space cause the space not to print reliably when exposed through the phase shifting mask alone. To alleviate this problem the system exposes the photoresist layer through the second mask, wherein the exposure through the second mask assists in exposing the space between the first feature and the second feature so that the space prints reliably.

Abstract: A structure and method are provided for correcting the optical proximity effects on a tri-tone attenuated phase-shifting mask. An attenuated rim, formed by an opaque region and an attenuated phase-shifting region, can be kept at a predetermined width across the mask or for certain types of structures. Typically, the attenuated rim is made as large as possible to maximize the effect of the attenuated phase-shifting region while still preventing the printing of larger portions of the attenuated phase-shifting region during the development process.

Abstract: One embodiment of the invention provides a system that facilitates optical proximity correction for alternating aperture phase shifting designs. During operation, the system receives a layout, which includes a complementary mask and a phase shifting mask. A subset of trim features on the complementary mask that are designed to protect the dark areas left unexposed by the phase shifting mask are adjusted first using a rules-based optical proximity correction process. This is then supplemented by a model-based correction to the phase shifters, Additionally, the portions of the trim that are co-extensive with the original layout can be corrected, e.g. at the time of the correction of the complementary mask using either rule or model based corrections.

Abstract: An automated phase assignment method is described that allows multiple rules for defining phase shifters to be used within a single cell. The rules for defining phase shifters can be sequenced. Then for a cell, the rules can be recursively applied. At each stage if the number of phase conflicts is below a threshold, then portions of the cell having conflicts are masked and processed using the next less aggressive rule set. This in turn leads to phase shifting masks with greater variation in phase shifter shapes and sizes. When the mask is used to fabricate integrated circuits (ICs), the resulting IC may have a greater number of small transistors and other features than a mask defined using only a single rule set per cell. Additional benefits can include better process latitude during IC fabrication and improved yield.

Abstract: One embodiment of the invention provides a system that performs optical proximity correction in a manner that accounts for properties of a mask writer that generates a mask used in printing an integrated circuit. During operation, the system receives an input layout for the integrated circuit. The system also receives a set of mask writer properties that specify how the mask writer prints features. Next, the system performs an optical proximity correction process on the input layout to produce an output layout that includes a set of optical proximity corrections. This optical proximity correction process accounts for the set of mask writer properties in generating the set of optical proximity corrections, so that the mask writer can accurately produce the set of optical proximity corrections.

Abstract: One embodiment of the invention provides a system that automatically resolves conflicts between phase shifters during creation of a phase shifting mask to be used in an optical lithography process for manufacturing an integrated circuit. Upon receiving a specification of a layout on the integrated circuit, the system identifies critical-dimension features within the layout. Next, the system places phase shifters comprised of phase shifting geometries on the phase shifting mask to precisely define the critical-dimension features. In doing so, the system identifies junctions within and/or between the critical-dimension features, and removes phase shifting geometries associated with the junctions to obviate coloring conflicts between phase shifters on the phase shifting mask. In one embodiment of the invention, the junctions include T-junctions and/or L-junctions.

Abstract: An approach to reducing the size of an output file generated by an optical proximity correction (OPC) process is described. An OPC output can be examined to identify identically sized segments with identical biases. Adjoining segments to those first identified to identify repeating basic shapes. Those basic shapes can be further refined and expanded as desired. Finally, the output is rewritten making use of the repeating shapes in a hierarchical output that places each shape once as a child cell of the original geometry and uses references to that shape in other locations thereby reducing data volume size. The data volume savings can be considerable.

Abstract: Processing a chip layout (e.g. optical proximity correction (OPC) or verification) can be time consuming and require the use of expensive tools. Organizing the original layout using segments can minimize both of these resources. For example, shapes within a unit can be dissected into segments. Each segment can be compared to segments stored in a database. If the segment matches a listed segment, then the segment can be linked to the listed segment. Matching can be done by identifying corners within a neighborhood of each segment. If the segment and its neighborhood do not match those of a listed segment, then a new database entry can be created. Only representative segments are used to perform processing, thereby significantly improving resource allocation. The results from the representative segments can be copied to their respective linked segments, thereby ensuring accuracy of the processing.

Abstract: A method and apparatus for providing correction for microloading effects is described. Hybrid proximity correction techniques are used to make the problem computationally more feasible. More specifically, feature edges in a layout can be grouped into those edges, or edge segments, with a large edge separation (group B), e.g. greater than n, and those having less than that separation (group A). The group B features can then be corrected for microloading effects rapidly using rules based correction. Then both groups of edges can be corrected using model based optical proximity correction using the output of the rule based correction as the ideal, or reference, layout.

Abstract: Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a mask file, to simulate the wafer exposure that the mask would provide under a given set of parameters. These parameters can relate to the mask itself, the inspection system used to create the mask file, and the stepper that can be used to expose the mask. The processes performed during the job can be done uniformly for defects on the mask. This uniformity allows the tool to efficiently run multiple jobs. The results of the job can be presented using different levels of detail to facilitate user review.

Abstract: Methods and apparatuses for fully defining static random access memory (SRAM) using phase shifting layouts are described. The approach includes identifying that a layout includes SRAM cells and defining phase shifting regions in a mask description to fully define the SRAM cells. The phase conflicts between adjacent phase shifters are resolved by selecting cutting patterns designed for the SRAM shape and functional structure. Additionally, the transistor gates of the SRAM cells can be reduced in size relative to the original SRAM layout design. Thus, an SRAM cell can be lithographically printed with small, consistent critical dimensions including extremely small gate lengths resulting in higher yields and improved performance.