Abstract: A mask defect printability simulation server provides simulations, one-dimensional analysis, and reports to multiple clients over a wide area network, such as the Internet. This network-based simulation server allows a client to leverage a core of highly-trained engineers. Additionally, the network-based simulation server can be easily supported since only a single source for the tools associated with the simulation server is necessary for multiple clients. A client can access the simulation server using a standard personal computer having a browser, thereby eliminating the need for client to maintain an expensive database for the server. Finally, in the network-based simulation server, multiple users can view the same mask defect image and provide real-time comments to each other as simulation and analysis are performed on the defect image, thereby encouraging problem solving and decision-making dialogue among the users.

Abstract: A reference image is generated from a subject image of at least a portion of a photolithography mask to enable a photolithography mask inspection and analysis system that otherwise cannot generate a reference image from a reference die or digitized design data, for example, to perform a mask analysis using the reference image. A mask inspection and analysis system may then be enhanced to perform one or more additional mask analyses to analyze the mask. The reference image is generated by identifying a defect or contaminant of the mask in the subject image and modifying the subject image to remove the defect or contaminant from the mask to generate the reference image. For one embodiment, a system using a STARlight inspection tool that captures transmitted and reflected images of a portion of a mask may then be enhanced to perform one or more mask analyses that use a reference image.

Abstract: One embodiment of the invention provides a system for reducing incidental exposure caused by phase shifting during fabrication of a semiconductor chip. The system operates by identifying a problem area of likely incidental exposure in close proximity to an existing phase shifter on a phase shifting mask, wherein the problem area includes a polysilicon line passing through a field region of the semiconductor chip. The system places an additional phase shifter into the problem area on the phase shifting mask so that a regulator within the additional phase shifter protects the polysilicon line passing through the field region. This additional phase shifter has a wider regulator than the existing phase shifter, wherein the existing phase shifter is used to expose a polysilicon line in a gate region of the semiconductor chip.

Abstract: One embodiment of the invention provides a method and a system for using phase shifter cutbacks to resolve conflicts between phase shifters during creation of a mask to be used in an optical lithography process for manufacturing an integrated circuit. The system works by locating a plurality of phase shifters, including a first phase shifter and a second phase shifter, on a phase shifting mask, and then identifying a conflict area wherein a conflict is likely to occur between the first phase shifter and the second phase shifter on the phase shifting mask. The system resolves this conflict by cutting back one or both of the first phase shifter and the second phase shifter, so that the first phase shifter and the second phase shifter do not interfere with each other in the conflict area.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: One embodiment of the invention provides a system that facilitates a semiconductor fabrication process to create a line end in a manner that controls line end shortening arising from optical effects, and is especially applicable in alternating aperture phase shifting. This system operates by positioning a first mask over a photoresist layer on a surface of a semiconductor wafer. This first mask includes opaque regions and transmissive regions that are organized into a first pattern that defines an unexposed line on the photoresist layer. The system then exposes the photoresist layer through the first mask. The system also positions a second mask over the photoresist layer on the surface of the semiconductor wafer. This second mask includes opaque regions and transmissive regions that are organized into a second pattern that defines an exposure region.

Abstract: A two mask process for small dimension features on an integrated circuit improves manufacturability and design tolerance. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.

Abstract: Design geometry information from an area outside the area of interest (AOI) on a mask can be combined with inspection information from the AOI to facilitate an accurate, simulated wafer image. The design geometry information can be easily generated or accessed, thereby ensuring an uninterrupted inspection process and minimizing the associated storage costs for the simulation process. The design geometry information can be pseudo design geometry information or actual design geometry information.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: A method of evaluating a stepper process affected by lens aberration is provided. The method includes receiving, from a facilitator responding to a request, a set of optical models including lens aberration information, wherein the lens aberration information is difficult to extract from the optical models. A decision can be made using the set of optical models. The decision could include determining which stepper(s) can be used (or should be avoided) with a mask, a layout, a process, and/or a chemistry. The decision could include ranking a plurality of steppers based on mask data to determine the best stepper (or next best steppers) to use.

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract: A system and method for optimizing the production of lithography reticles involves identifying “proximity effect halos” around tight tolerance features in an IC layout data file. Features and defects outside the halos will not have a significant effect on the printing of the tight tolerance features. During reticle formation, the tight tolerance features and associated halos can be carefully written and inspected to ensure accuracy while the other portions of the reticle can be written/inspected less stringently for efficiency. The halo width can be determined empirically or can be estimated by process modeling. If an electron beam tool is used to write the reticle, a small spot size can be used to expose the tight tolerance features and the halos, whereas a large spot size can be used to expose the remainder of the reticle. A reticle production system can include a computer to read an IC layout data file, identify tight tolerance features, and define proximity effect halos.

Abstract: One embodiment of the invention provides a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit. The system operates by receiving a specification of the integrated circuit, wherein the specification defines transistors that include gates. Next, the system identifies a gate within the specification, wherein the gate includes an endcap that is susceptible to line end shortening during the optical lithography process. The system then extends a phase shifter used to form the gate, so that the phase shifter defines at least a portion of the endcap and thereby reduces line end shortening of the endcap due to optical effects.

Abstract: A structure and method are provided to ensure self-aligned fabrication of a tri-tone attenuated phase-shifting mask. A sub-resolution, 0 degree phase, greater than 90% transmission rim is provided along the edge of an opaque region. The alignment of this sub-resolution rim with the opaque and attenuated regions of the mask is performed in a single patterning step. In one embodiment, a narrow opaque region can be replaced by a sub-resolution, 0 degree phase, greater than 90% transmission line.

Abstract: An accurate, cost-effective system and method for correcting 3D effects on an alternating phase-shifting mask (PSM) is provided. To facilitate this correction, a library can be built to include a first group of 180 degree phase-shifting regions, wherein these regions have a common first size. Based on this first size, 3D simulation is performed. A transmission and a phase are altered in a 2D simulation based on this first size until a shape dependent transmission and a shape dependent phase allow the 2D simulation to substantially match the 3D simulation. Finally, a modified first size is chosen using the shape dependent transmission and the shape dependent phase such that a 2D simulation based on the modified first size substantially matches the 3D simulation based on the first size. The library associates the first size with the modified first size, the shape dependent transmission, and the shape dependent phase.

Abstract: One embodiment of the invention provides a system that automatically resolves conflicts between phase shifters during creation of a phase shifting mask to be used in an optical lithography process for manufacturing an integrated circuit. Upon receiving a specification of a layout on the integrated circuit, the system identifies critical-dimension features within the layout. Next, the system places phase shifters comprised of phase shifting geometries on the phase shifting mask to precisely define the critical-dimension features. In doing so, the system identifies junctions within and/or between the critical-dimension features, and removes phase shifting geometries associated with the junctions to obviate coloring conflicts between phase shifters on the phase shifting mask. In one embodiment of the invention, the junctions include T-junctions and/or L-junctions.

Abstract: A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.

Abstract: One embodiment of the invention provides a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit. The system operates by receiving a specification of the integrated circuit, wherein the specification defines transistors that include gates. Next, the system identifies a gate within the specification, wherein the gate includes an endcap that is susceptible to line end shortening during the optical lithography process. The system then extends a phase shifter used to form the gate, so that the phase shifter defines at least a portion of the endcap and thereby reduces line end shortening of the endcap due to optical effects.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

Abstract: Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table.