Abstract: Design rule checking (DRC) can be applied to a mask layout using a shape-based system. A shape includes a set of associated edges in a specified configuration. Design rules can then be based on various shapes, advantageously enabling efficient formulation and precise application of design rules. A concurrent processing methodology can be used to minimize processing overhead during this rule application. Design rules can also be incorporated into a lookup table (LUT) to further reduce DRC runtime by substantially minimizing the number of times a design rule must actually be calculated. A LUT can also improve DRC runtime for edge-based, concurrent processing DRC systems. A DRC system can also be connected to a network across which design rules and mask layout data files can be accessed and retrieved.

Abstract: One embodiment of the invention provides a system to facilitate visualization of optical proximity corrections to a circuit layout. This system operates by receiving an input circuit layout and a set of optical proximity correction parameters. The system performs an optical proximity correction on this input circuit layout using the set of optical proximity correction parameters. The output of the optical proximity correction process includes an output circuit layout with optical proximity corrections. This output also includes additional information that allows a user to visualize how the set of optical proximity corrections were determined. Notably, the additional information can be stored in the same representation as the output circuit layout and viewed with the same viewer used for viewing the output circuit layout.

Abstract: A technique for forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, includes identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. An evaluation point is determined for the edge based on a first target length for corner segments, a second target length for non-corner segments, and characteristics of the edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point. Another technique determines an edge type of the edge of the polygon based on the first target length for corner segments, the second target length for non-corner segments, and the characteristics of the edge. Then, the edge is divided into segments based on the edge type and the characteristics of the edge.

Abstract: Methods and apparatuses for preparing layouts and masks that use phase shifting to enable production of subwavelength features on an integrated circuit in close (optical) proximity to other structures are described. One embodiment selects from several strategies for resolving conflicts between phase shifters used to define features and (optically) proximate structures that are being defined other than by phase shifting. One embodiment adds additional phase shifters to define the conflicting structures. Another embodiment corrects the shape of the phase shifters in proximity to a conflicting structure. Resulting integrated circuits can include a greater number of subwavelength features even in areas that are in close proximity to structures that were not initially identified for production using a phase shifting mask.

Abstract: One embodiment of the invention provides a system for analyzing a layout related to a circuit on a semiconductor chip. The system operates by receiving a design hierarchy specifying the layout of the circuit. This layout includes a set of hierarchically organized nodes, wherein a given node specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy. The system operates by modifying the design hierarchy by examining a set of sibling nodes that are located under a parent node in the design hierarchy in order to identify a set of interacting geometrical features between the set of sibling nodes. Next, the system then moves the set of interacting geometrical features to a new child node under the parent node, and then performs an analysis on the modified design hierarchy.

Abstract: One embodiment of the invention provides a system for analyzing a layout related to a circuit on a semiconductor chip. The system operates by receiving a design hierarchy specifying the layout of the circuit. This design hierarchy includes a set of hierarchically organized nodes, wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy. The system modifies the design hierarchy by, examining a set of sibling nodes that are located under a parent node in the design hierarchy in order to identify a set of interacting geometrical features between the set of sibling nodes. The system then moves the set of interacting geometrical features from the sibling nodes to the parent node, so that the interaction is visible at the parent node.

Abstract: A method and apparatus for providing correction for microloading effects is described. Hybrid proximity correction techniques are used to make the problem computationally more feasible. More specifically, feature edges in a layout can be grouped into those edges, or edge segments, with a large edge separation (group B), e.g. greater than n, and those having less than that separation (group A). The group B features can then be corrected for microloading effects rapidly using rules based correction. Then both groups of edges can be corrected using model based optical proximity correction using the output of the rule based correction as the ideal, or reference, layout.

Abstract: Automated techniques for identifying dummy/main features on a mask layer are provided. In a multiple mask layer technique, the definition of a dummy/main feature can be based on connectivity information or functional association information. In a geometry technique, the definition of a dummy/main feature can be based on a feature size, a feature shape, a pattern of features, or a proximity of a feature to a neighboring feature. In one embodiment, multiple definitions and multiple techniques can be used.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

Abstract: Methods and apparatuses for preparing layouts and masks that use phase shifting to enable production of subwavelength features on an integrated circuit in close (optical) proximity to other structures are described. One embodiment selects from several strategies for resolving conflicts between phase shifters used to define features and (optically) proximate structures that are being defined other than by phase shifting. One embodiment adds additional phase shifters to define the conflicting structures. Another embodiment optically corrects the shape of the phase shifters in proximity to a conflicting structure. Resulting integrated circuits can include a greater number of subwavelength features even in areas that are in close proximity to structures that were not initially identified for production using a phase shifting mask.

Abstract: Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table. The bias table can include both rule-based and model-based actions, and can also include single-edge shapes for completeness. The scanning of the IC layout can be performed in order of increasing or decreasing complexity, or can be specified by the user.

Abstract: Phase shifting layouts and masks with phase conflicts are described. The phase shifting layout defines light transmissive regions for use in defining selected features in a layer of material of an integrated circuit (IC). The phase shifting layout includes a phase conflict caused by two light transmissive regions that are out of phase with each other and which, without correction, would lead to the definition of an artifact in the layer of material. A corresponding mask adapted for use in conjunction with the phase shifting mask can ensure that the artifact is ultimately erased. The phase conflict is intentionally introduced into the phase shifting layout during phase assignment to permit all of the selected features to be defined using the phase shifting mask.

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract: A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated.

Abstract: Methods and apparatuses for preparing layouts and masks that use phase shifting to enable production of subwavelength features on an integrated circuit in close (optical) proximity to other structures are described. One embodiment selects from several strategies for resolving conflicts between phase shifters used to define features and (optically) proximate structures that are being defined other than by phase shifting. One embodiment adds additional phase shifters to define the conflicting structures. Another embodiment optically corrects the shape of the phase shifters in proximity to a conflicting structure. Resulting integrated circuits can include a greater number of subwavelength features even in areas that are in close proximity to structures that were not initially identified for production using a phase shifting mask.

Abstract: A method extends the use of phase shift techniques to complex layouts, and includes identifying a pattern, and automatically mapping the phase shifting regions for implementation of such features. The pattern includes small features having a dimension smaller than a first particular feature size, and at least one relatively large feature, the at least one relatively large feature and another feature in the pattern having respective sides separated by a narrow space. Phase shift regions are laid out including a first set of phase shift regions to define said small features, and a second set of phase shift regions to assist definition of said side of said relatively large feature. An opaque feature is used to define the relatively large feature, and a phase shift region in the second set is a sub-resolution window inside the perimeter of the opaque feature.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. In one approach, phase shift regions are laid out so that they extend around corners in a feature, and in one or more identified corners having greater process latitude, the phase shift regions are divided and assigned opposite phases in the corner.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

Abstract: One embodiment of the invention provides a system for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip. This system operates by receiving a design hierarchy specifying the layout of the circuit, wherein the design hierarchy includes a set of hierarchically organized nodes. Within this design hierarchy, a given node specifies a geometrical feature, which can be comprised of lower-level geometrical features. These lower-level geometrical features are represented by lower-level nodes that appear under the given node in the design hierarchy. Furthermore, the layout of the given node is specified by a first cell, which in turn specifies the layout of one or more nodes in the design hierarchy. For each node within the design hierarchy, the system determines how interactions with the node's siblings and/or parent, and possibly other surrounding geometries, change the layout of the node as specified by the first cell.

Abstract: A photolithographic mask used for defining a layer in an integrated circuit, or other work piece, where the layer comprises a pattern including a plurality of features to be implemented with phase shifting in phase shift regions is laid out including for patterns comprising high density, small dimension features, and for “full shift” patterns. The method includes identifying cutting areas for phase shift regions based on characteristics of the pattern. Next, the process cuts the phase shift regions in selected ones of the cutting areas to define phase shift windows, and assigns phase values to the phase shift windows. The phase shift values assigned comprise &phgr; and &thgr;, so that destructive interference is caused in transitions between adjacent phase shift windows having respective phase shift values of &phgr; and &thgr;. In the preferred embodiment, &phgr; is equal to approximately &thgr;+180 degrees.