Abstract: PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

Abstract: Candidate drug exploration processes utilizing a masked discrete diffusion model with fragment remasking to generate molecular sequences, wherein the operation of the masked discrete diffusion model is conditioned with molecular context guidance, and fragment remasking involves generating molecular fragment candidates, masking the molecular fragment candidates, scoring the molecular fragment candidates, and attaching the molecular fragment candidates to a molecule.

Abstract: Circuits for mitigating noise and droop on supply rails that utilize a clock stretcher that includes a chain of adjustable delay elements configured to generate multiple phases of the first clock signal. The circuits are configured to select from among the phases of the first clock signal to form a second clock signal that is a stretched, glitchless form of the first clock signal.

Abstract: An integrated circuit die binning process involves forming a batch of singulated die, configuring intersection regions of a multi-dimensional control structure with settings indicating die grouping compatibility, identifying a first die with the lowest die grouping compatibility, and randomly selecting a second die for grouping with the first die or voiding the first die from one dimension of the control structure, repeating these actions for more die from the batch.

Abstract: Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code.

Abstract: Mechanisms to improve the thermal conductivity of three-dimensional integrated circuit (3DIC) structures by thinning the metal and dielectric layers in comparison to the dimensions of these layers in conventional 3DIC structures, resulting in a commensurate thinning of the oxide layers between active layers and metal layers, and a reduction in the number of metal and oxide layers utilized compared to conventional 3DIC structures.

Abstract: Mechanisms to tune resonant frequencies of the resonators in a double resonator structure that includes a first resonator and a second resonator utilizing logic to operate tuning elements to align a dip in the circulating power in the first resonator with a peak in the drop port power of the second resonator.

Abstract: An integrated circuit die binning process involves forming a batch of singulated die, configuring intersection regions of a multi-dimensional control structure with settings indicating die grouping compatibility, identifying a first die with the lowest die grouping compatibility, and randomly selecting a second die for grouping with the first die or voiding the first die from one dimension of the control structure, repeating these actions for more die from the batch.

Abstract: Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a first fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code. A second fast-propagation path is configured to propagate a second code to the digitally controlled oscillator.

Abstract: Metal track reduction mechanisms in systems utilizing an address bus wherein an address decoder is configured to operate on a first subset of applied address bits and a Gray Coder is configured to operate on a second subset of the applied address bits to generate a Gray Code. A sequence of inverters is configured to invert a bit of the Gray Code at multiple locations along the address bus, each location corresponding to a component to select with the applied address.

Abstract: Feedforward reasoning models that include a video encoder configured to generate feature tokens from an input video, logic to condition the feature tokens with camera parameters, at least one sparse attention head with two-way attention to transform settings from the feature tokens into a tracking token, a depth token, and a visibility token in accordance with an input prompt, and logic configured to transform the tracking token, depth token, and visibility token into track predictions for an object specified by the input prompt.

Abstract: Generalizable feature distillation systems that align 3D features with 2D foundation model features using a feedforward network, avoiding per-scene optimization, and a flexible end-to-end 3D scene interpretation system that applies the extracted 3D features and pretrained 2D vision-language models for various 3D scene understanding tasks.

Abstract: Feedforward reasoning models that include a video encoder configured to generate feature tokens from an input video, at least one dense attention head, at least one sparse attention head with two-way attention logic configured to transform settings from the feature tokens into a tracking token, a depth token, and a visibility token in accordance with an input prompt, and logic configured to transform the tracking token, depth token, and visibility token into track predictions for an object specified by the input prompt.

Abstract: Systems including a pelvis depth estimation model configured to generate a pelvis depth estimate of a person depicted in an image, a human mesh estimation model configured to generate a body mesh corresponding to the person depicted in the image given the estimated pelvis depth, and a camera solver configured to apply differentiable rasterization to derive camera parameters for the image.

Abstract: Systems including a power supply and multiple chips or die, wherein settings may be configured that when applied to a first one of the chips or die configure the first chip or die to associate a power allocation limit with at least a second one of the chips or die, wherein a sum of the power allocation limit and a power consumption limit of the first chip or die exceeds a total power capacity of the power supply. The systems operate the first chip or die at a lower priority than the other chips or die for receiving operating power from the power supply, and the first chip or die is operated as a master controller of allocation of the operating power from the power supply to the first chip or die and to the other chips or die.

Abstract: A circuit includes a bandgap circuit configured to generate multiple reference voltages. A first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail.

Abstract: Adaptive clock mechanisms for serial links utilizing a delay-chain-based edge generation circuit to generate a clock that is a faster (higher-frequency) version of an incoming digital clock. The base frequency of the link clock utilized by the line transmitters is determined by the (slower) clock utilized by the digital circuitry supplying data to the line transmitters. An edge generator that may be composed of only non-synchronous circuit elements multiplies the edges of the slower clock to generate the link clock and also a clock forwarded to the receiver at a phase offset from the link clock.

Abstract: Reverse offload mechanisms that utilize a second processor to receiving a workload from a first processor, the workload including multiple tasks, where the second processor collects portions of the tasks from a set of co-executing threads in the second processor and dispatches portions of the tasks to queues for threads of the first processor, and in response to one or more of status indications satisfying a completion condition for the first portions of the tasks, combines first partial results of the tasks from the set of co-executing threads with second partial results of the portions of the tasks from the first processor.

Abstract: Text-to-image transformers configured in one aspect to associate an input text token with the specific object, apply latent blending with attention to a combination of keys and values for the input text token and a background image upon which to add the object; and which in another aspect perform latent blending with attention to keys and values for the object to add, keys and values for the background, and keys and values for a text prompt.

Abstract: Devices including an arrangement of multiple of physically unclonable function (PUF) cells organized to generate a bit pattern, and wherein the PUF cells each includes multiple inverting stages, each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters.