Abstract: Physically unclonable function cells based on bit-storing machine-memory circuits include a pair of parallel circuit branches, each of the parallel branches including a first transistor configured to be always-ON when the physically unclonable function cell is powered, and a second transistor cross-coupled to an opposite one of the parallel branches.

Abstract: An optical transmitter includes lasers configured to generate a wave division multiplex (WDM) on a light guide, and a Code Division Multiple Access (CDMA) symbol generator coupled to modulate CDMA symbols on the light guide across the channels of the WDM. The transmitter utilizes of laser locking controls configured to correlate the CDMA symbols to frequency adjustments applied to the lasers.

Abstract: An optical communication system includes at least one wave division multiplex (WDM) transmitter configured to generate WDM signals in multiple channels on a light guide, and a Code Division Multiple Access (CDMA) symbol generator coupled to modulate output of the WDM transmitter at a frequency below a noise floor of the WDM signals.

Abstract: Optical transceiver architecture utilizing micro-ring modulators and micro-ring resonators configured to route resonant wavelengths of light injected into each micro-ring resonator's input port and through port to that micro-ring resonator's drop port and add port, respectively. The micro-ring resonators drop two distinct streams of data modulated onto the same optical wavelength, or two wavelengths separated by an integer number of free spectral ranges coupled into the micro-ring resonators in two different directions.

Abstract: Devices including an arrangement of multiple of physically unclonable function (PUF) cells organized to generate a bit pattern, and wherein the PUF cells each includes multiple inverting stages, each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters.

Abstract: Mechanisms for implementing text-to-volumetric video transformers utilizing a first stage configured to transform a text prompt into a three-dimensional neural radiance field, and a second stage configured to apply a four-dimensional multi-resolution deformation field to generate time-varying displacements for the three-dimensional neural radiance field consistent with motion expressed in the text prompt, while maintaining a content of the three-dimensional neural radiance field static.

Abstract: Graph-based mechanisms to model and control the synthesis of circuits on a layer basis, including a deep learning model trained on light-weight graph structures rather than complex circuit designs encoded in collateral files generated by EDA systems, and utilizing graph-based algorithms one the graph structure to determine candidate circuit structures and synthesis processes.

Abstract: Mechanisms for the generation of randomized sequences of substantial length the generation of which involves the frequent exchange of long bit sequences between threads in a multiprocessor. The mechanisms accelerate in hardware the swapping of long sequences between threads that in conventional systems slows the generation of the sequences down and increases the power consumption needed to generate the sequences.

Abstract: Inter-process communication methods that divide a total payload of a first memory command among a plurality of packets and that encode a last-transmitted packet of the plurality of packets to include a metadata code in the total payload. The memory command may be communicated between processes executing a collective operation. Payloads of the packets are written to memory in a sequential address order, such that the metadata code is written to a particular address, and the second process generates an acknowledgment of the first memory command to the first process on condition that reading the particular address returns the metadata code.

Abstract: Video-based multimodal large language models that include an image encoder configured to transform frames from a video into visual tokens, a multimodal large language model configured to receive the visual tokens, and a temporal module interposed between the image encoder and the multimodal large language model.

Abstract: PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

Abstract: Circuits for mitigating noise and droop on supply rails that utilize a clock stretcher that includes a chain of adjustable delay elements configured to generate multiple phases of the first clock signal. The circuits are configured to select from among the phases of the first clock signal to form a second clock signal that is a stretched, glitchless form of the first clock signal.

Abstract: Candidate drug exploration processes utilizing a masked discrete diffusion model with fragment remasking to generate molecular sequences, wherein the operation of the masked discrete diffusion model is conditioned with molecular context guidance, and fragment remasking involves generating molecular fragment candidates, masking the molecular fragment candidates, scoring the molecular fragment candidates, and attaching the molecular fragment candidates to a molecule.

Abstract: An integrated circuit die binning process involves forming a batch of singulated die, configuring intersection regions of a multi-dimensional control structure with settings indicating die grouping compatibility, identifying a first die with the lowest die grouping compatibility, and randomly selecting a second die for grouping with the first die or voiding the first die from one dimension of the control structure, repeating these actions for more die from the batch.

Abstract: Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code.

Abstract: Mechanisms to improve the thermal conductivity of three-dimensional integrated circuit (3DIC) structures by thinning the metal and dielectric layers in comparison to the dimensions of these layers in conventional 3DIC structures, resulting in a commensurate thinning of the oxide layers between active layers and metal layers, and a reduction in the number of metal and oxide layers utilized compared to conventional 3DIC structures.

Abstract: Mechanisms to tune resonant frequencies of the resonators in a double resonator structure that includes a first resonator and a second resonator utilizing logic to operate tuning elements to align a dip in the circulating power in the first resonator with a peak in the drop port power of the second resonator.

Abstract: An integrated circuit die binning process involves forming a batch of singulated die, configuring intersection regions of a multi-dimensional control structure with settings indicating die grouping compatibility, identifying a first die with the lowest die grouping compatibility, and randomly selecting a second die for grouping with the first die or voiding the first die from one dimension of the control structure, repeating these actions for more die from the batch.

Abstract: Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a first fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code. A second fast-propagation path is configured to propagate a second code to the digitally controlled oscillator.

Abstract: Metal track reduction mechanisms in systems utilizing an address bus wherein an address decoder is configured to operate on a first subset of applied address bits and a Gray Coder is configured to operate on a second subset of the applied address bits to generate a Gray Code. A sequence of inverters is configured to invert a bit of the Gray Code at multiple locations along the address bus, each location corresponding to a component to select with the applied address.