Abstract: Mechanisms to process multi-view RGB images and object masks into an inpainted Gaussian representation with removed objects, wherein occluded regions are consistently inpainted across views. A diffusion model trained with object masks in operated to remove objects from the scene and refined unseen mask generation, depth-aware Gaussian initialization, and SDEdit-like RGB detail enhancement are performed to produce the final rendered views.

Abstract: A circuit includes a bandgap circuit configured to generate multiple reference voltages. A first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail.

Abstract: Cold plate embodiments utilizing a vapor chamber formed with a vapor conduit and top and bottom heat exchangers that direct coolant across surfaces of the vapor chamber to conduct heat away from a device to cool, such as an integrated circuit. The cold plate may receive pumped coolant via multiple low-profile inlet ports, and the coolant may exit the cold plate via multiple low-profile outlet ports.

Abstract: Apparatus including a body formed with a pivot surface and multiple lever arms arranged along the pivot surface, each lever arm formed such that the body forms an acute angle of engagement with a chassis when the pivot surface contacts the chassis and a distal end of the lever arms contacts an underside of a board mounted parallel to the chassis and an arc of the lever arms contacts an edge of the board.

Abstract: Mechanisms are described for throttling the resource demands of multiple system components. For each of the components generating demands to use a shared system resource, at least one time interval is configured, and during the time interval indications of whether the resource is over-utilized or under-utilized and sampled. After a conclusion of the time interval, the time interval of every component is expanded or is contracted, as determined by the indications.

Abstract: Simultaneous bi-directional transceivers that include a main transmit driver, a replica transmit driver, and either a tri-capacitance network or a resistive-bi-capacitance network, wherein the replica transmit driver may be configured to receive an inverted form of a signal received by the main transmit driver, and a delay path for the main transmit driver may be configured to provide more precise tuning of signal delay than a delay path of the replica transmit driver.

Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.

Abstract: Circuits for mitigating noise and droop on supply rails that utilize a clock stretcher that includes a chain of adjustable delay elements configured to generate multiple phases of the first clock signal. The circuits are configured to select from among the phases of the first clock signal to form a second clock signal that is a stretched, glitchless form of the first clock signal.

Abstract: Physically unclonable function cells based on bit-storing machine-memory circuits include a pair of parallel circuit branches, each of the parallel branches including a first transistor configured to be always-ON when the physically unclonable function cell is powered, and a second transistor cross-coupled to an opposite one of the parallel branches.

Abstract: An optical transmitter includes lasers configured to generate a wave division multiplex (WDM) on a light guide, and a Code Division Multiple Access (CDMA) symbol generator coupled to modulate CDMA symbols on the light guide across the channels of the WDM. The transmitter utilizes of laser locking controls configured to correlate the CDMA symbols to frequency adjustments applied to the lasers.

Abstract: An optical communication system includes at least one wave division multiplex (WDM) transmitter configured to generate WDM signals in multiple channels on a light guide, and a Code Division Multiple Access (CDMA) symbol generator coupled to modulate output of the WDM transmitter at a frequency below a noise floor of the WDM signals.

Abstract: Optical transceiver architecture utilizing micro-ring modulators and micro-ring resonators configured to route resonant wavelengths of light injected into each micro-ring resonator's input port and through port to that micro-ring resonator's drop port and add port, respectively. The micro-ring resonators drop two distinct streams of data modulated onto the same optical wavelength, or two wavelengths separated by an integer number of free spectral ranges coupled into the micro-ring resonators in two different directions.

Abstract: Devices including an arrangement of multiple of physically unclonable function (PUF) cells organized to generate a bit pattern, and wherein the PUF cells each includes multiple inverting stages, each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters.

Abstract: Mechanisms for implementing text-to-volumetric video transformers utilizing a first stage configured to transform a text prompt into a three-dimensional neural radiance field, and a second stage configured to apply a four-dimensional multi-resolution deformation field to generate time-varying displacements for the three-dimensional neural radiance field consistent with motion expressed in the text prompt, while maintaining a content of the three-dimensional neural radiance field static.

Abstract: Graph-based mechanisms to model and control the synthesis of circuits on a layer basis, including a deep learning model trained on light-weight graph structures rather than complex circuit designs encoded in collateral files generated by EDA systems, and utilizing graph-based algorithms one the graph structure to determine candidate circuit structures and synthesis processes.

Abstract: Mechanisms for the generation of randomized sequences of substantial length the generation of which involves the frequent exchange of long bit sequences between threads in a multiprocessor. The mechanisms accelerate in hardware the swapping of long sequences between threads that in conventional systems slows the generation of the sequences down and increases the power consumption needed to generate the sequences.

Abstract: Video-based multimodal large language models that include an image encoder configured to transform frames from a video into visual tokens, a multimodal large language model configured to receive the visual tokens, and a temporal module interposed between the image encoder and the multimodal large language model.

Abstract: Inter-process communication methods that divide a total payload of a first memory command among a plurality of packets and that encode a last-transmitted packet of the plurality of packets to include a metadata code in the total payload. The memory command may be communicated between processes executing a collective operation. Payloads of the packets are written to memory in a sequential address order, such that the metadata code is written to a particular address, and the second process generates an acknowledgment of the first memory command to the first process on condition that reading the particular address returns the metadata code.

Abstract: PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

Abstract: Circuits for mitigating noise and droop on supply rails that utilize a clock stretcher that includes a chain of adjustable delay elements configured to generate multiple phases of the first clock signal. The circuits are configured to select from among the phases of the first clock signal to form a second clock signal that is a stretched, glitchless form of the first clock signal.