Abstract: Mechanisms to generate surprise potentials that may be utilized to configure autonomous vehicle control logic, the surprise potentials derived from a shift between trajectory distributions generated by a trajectory prediction model having a feedforward prediction structure or diffusion-based structure, and counterfactual trajectory distributions based upon the trajectory distributions of the prediction model.

Abstract: Mechanisms for configuring a humanoid robot comprising a plurality of multi-fingered graspers to perform dexterous manipulation tasks, whereby a plurality of simulated environments are generated representing a distribution of kinematic parameter combinations corresponding to a physical robot. In each simulated environment, a target trajectory sequence recorded from the physical robot is executed. For each simulated environment, a tracking error relative to execution of the target trajectory sequence by the physical robot is calculated. One or more simulated environments are selected based on a minimization of an average squared difference between simulated tracking error and real-world tracking error, and a manipulation policy for the physical robot is then trained within the selected simulated environments using reinforcement learning.

Abstract: A regulator for a load voltage includes a pass transistor for a load current, a gate voltage sensor coupled to a gate of the pass transistor, and a feed-forward supply noise cancellation circuit configured to amplify a gain of a supply noise cancelling signal at increments of the gate voltage.

Abstract: Optical circuit architectures utilizing primary laser light sources and at least one auxiliary laser light source. The primary lasers may be fixed-wavelength lasers and/or comb lasers, and the auxiliary lasers may be fixed-wavelength lasers, tunable-wavelength lasers, and/or comb lasers. In some cases optical switches are utilized along the optical paths in various configurations between the laser inputs and output terminals of the optical paths or between the laser inputs and a transform network.

Abstract: Two and three dimensional video diffusion models configured via training to be equivariant to spatial transformations of the input by training the model using warped noise, where equivariance of the models is learned using a conventional video diffusion loss function modified to replace independent noise inputs with warped noise inputs.

Abstract: A process for manufacturing inductors for use in integrated circuits includes embedding ferromagnetic material in a bulk silicon substrate, forming a plurality of vias in the bulk silicon substrate such that the vias bracket a volume of the bulk silicon substrate that includes the ferromagnetic material, slicing the bulk silicon substrate to form a silicon wafer, and configuring traces between top metal pads of the vias and between bottom metal pads of the vias to form a continuous path for current to flow circumferentially from a first end of the volume to a second end of the volume.

Abstract: A graph neural network for average power estimation of netlists is trained with register toggle rates over a power window from an RTL simulation and gate level netlists as input features. Combinational gate toggle rates are applied as labels. The trained graph neural network is then applied to infer combinational gate toggle rates over a different power window of interest and/or different netlist.

Abstract: An optical communication system includes at least one wave division multiplex (WDM) transmitter configured to generate WDM signals in multiple channels on a light guide, and a Code Division Multiple Access (CDMA) symbol generator coupled to modulate output of the WDM transmitter at a frequency below a noise floor of the WDM signals.

Abstract: Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code.

Abstract: Self-supervised machine learning is applied to combinational gate sizing based on an input circuit netlist. A transformer neural network architecture is disclosed to select gate sizes along paths of the network between primary inputs/outputs and/or sequential logic elements. The gate size selections may be optimized along dimensions such as path delay, path power consumption, and path circuit area.

Abstract: Mechanisms to process multi-view RGB images and object masks into an inpainted Gaussian representation with removed objects, wherein occluded regions are consistently inpainted across views. A diffusion model trained with object masks in operated to remove objects from the scene and refined unseen mask generation, depth-aware Gaussian initialization, and SDEdit-like RGB detail enhancement are performed to produce the final rendered views.

Abstract: A circuit includes a bandgap circuit configured to generate multiple reference voltages. A first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail.

Abstract: Cold plate embodiments utilizing a vapor chamber formed with a vapor conduit and top and bottom heat exchangers that direct coolant across surfaces of the vapor chamber to conduct heat away from a device to cool, such as an integrated circuit. The cold plate may receive pumped coolant via multiple low-profile inlet ports, and the coolant may exit the cold plate via multiple low-profile outlet ports.

Abstract: Apparatus including a body formed with a pivot surface and multiple lever arms arranged along the pivot surface, each lever arm formed such that the body forms an acute angle of engagement with a chassis when the pivot surface contacts the chassis and a distal end of the lever arms contacts an underside of a board mounted parallel to the chassis and an arc of the lever arms contacts an edge of the board.

Abstract: Mechanisms are described for throttling the resource demands of multiple system components. For each of the components generating demands to use a shared system resource, at least one time interval is configured, and during the time interval indications of whether the resource is over-utilized or under-utilized and sampled. After a conclusion of the time interval, the time interval of every component is expanded or is contracted, as determined by the indications.

Abstract: Simultaneous bi-directional transceivers that include a main transmit driver, a replica transmit driver, and either a tri-capacitance network or a resistive-bi-capacitance network, wherein the replica transmit driver may be configured to receive an inverted form of a signal received by the main transmit driver, and a delay path for the main transmit driver may be configured to provide more precise tuning of signal delay than a delay path of the replica transmit driver.

Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.

Abstract: Circuits for mitigating noise and droop on supply rails that utilize a clock stretcher that includes a chain of adjustable delay elements configured to generate multiple phases of the first clock signal. The circuits are configured to select from among the phases of the first clock signal to form a second clock signal that is a stretched, glitchless form of the first clock signal.

Abstract: Physically unclonable function cells based on bit-storing machine-memory circuits include a pair of parallel circuit branches, each of the parallel branches including a first transistor configured to be always-ON when the physically unclonable function cell is powered, and a second transistor cross-coupled to an opposite one of the parallel branches.

Abstract: An optical transmitter includes lasers configured to generate a wave division multiplex (WDM) on a light guide, and a Code Division Multiple Access (CDMA) symbol generator coupled to modulate CDMA symbols on the light guide across the channels of the WDM. The transmitter utilizes of laser locking controls configured to correlate the CDMA symbols to frequency adjustments applied to the lasers.