Abstract: Feedforward reasoning models that include a video encoder configured to generate feature tokens from an input video, logic to condition the feature tokens with camera parameters, at least one sparse attention head with two-way attention to transform settings from the feature tokens into a tracking token, a depth token, and a visibility token in accordance with an input prompt, and logic configured to transform the tracking token, depth token, and visibility token into track predictions for an object specified by the input prompt.

Abstract: Feedforward reasoning models that include a video encoder configured to generate feature tokens from an input video, at least one dense attention head, at least one sparse attention head with two-way attention logic configured to transform settings from the feature tokens into a tracking token, a depth token, and a visibility token in accordance with an input prompt, and logic configured to transform the tracking token, depth token, and visibility token into track predictions for an object specified by the input prompt.

Abstract: Generalizable feature distillation systems that align 3D features with 2D foundation model features using a feedforward network, avoiding per-scene optimization, and a flexible end-to-end 3D scene interpretation system that applies the extracted 3D features and pretrained 2D vision-language models for various 3D scene understanding tasks.

Abstract: Systems including a pelvis depth estimation model configured to generate a pelvis depth estimate of a person depicted in an image, a human mesh estimation model configured to generate a body mesh corresponding to the person depicted in the image given the estimated pelvis depth, and a camera solver configured to apply differentiable rasterization to derive camera parameters for the image.

Abstract: Systems including a power supply and multiple chips or die, wherein settings may be configured that when applied to a first one of the chips or die configure the first chip or die to associate a power allocation limit with at least a second one of the chips or die, wherein a sum of the power allocation limit and a power consumption limit of the first chip or die exceeds a total power capacity of the power supply. The systems operate the first chip or die at a lower priority than the other chips or die for receiving operating power from the power supply, and the first chip or die is operated as a master controller of allocation of the operating power from the power supply to the first chip or die and to the other chips or die.

Abstract: A circuit includes a bandgap circuit configured to generate multiple reference voltages. A first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail.

Abstract: Reverse offload mechanisms that utilize a second processor to receiving a workload from a first processor, the workload including multiple tasks, where the second processor collects portions of the tasks from a set of co-executing threads in the second processor and dispatches portions of the tasks to queues for threads of the first processor, and in response to one or more of status indications satisfying a completion condition for the first portions of the tasks, combines first partial results of the tasks from the set of co-executing threads with second partial results of the portions of the tasks from the first processor.

Abstract: Adaptive clock mechanisms for serial links utilizing a delay-chain-based edge generation circuit to generate a clock that is a faster (higher-frequency) version of an incoming digital clock. The base frequency of the link clock utilized by the line transmitters is determined by the (slower) clock utilized by the digital circuitry supplying data to the line transmitters. An edge generator that may be composed of only non-synchronous circuit elements multiplies the edges of the slower clock to generate the link clock and also a clock forwarded to the receiver at a phase offset from the link clock.

Abstract: Text-to-image transformers configured in one aspect to associate an input text token with the specific object, apply latent blending with attention to a combination of keys and values for the input text token and a background image upon which to add the object; and which in another aspect perform latent blending with attention to keys and values for the object to add, keys and values for the background, and keys and values for a text prompt.

Abstract: Devices including an arrangement of multiple of physically unclonable function (PUF) cells organized to generate a bit pattern, and wherein the PUF cells each includes multiple inverting stages, each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters.

Abstract: Circuits for mitigating noise and droop on supply rails that utilize a clock stretcher that includes a chain of adjustable delay elements configured to generate multiple phases of the first clock signal. The circuits are configured to select from among the phases of the first clock signal to form a second clock signal that is a stretched, glitchless form of the first clock signal.

Abstract: Systems including a first resonator and a second resonator disposed along a waveguide at an output of at least one laser configured to generate a multi-channel optical spectrum, and logic configured to tune the first resonator to a first sideband channel of a multi-channel optical spectrum, tune the second resonator to a second sideband channel of the multi-channel optical spectrum, monitor the first resonator and the second resonator for a common mode wavelength signal of the first sideband channel and the second sideband channel, and apply the common mode wavelength signal to control resonant frequencies of resonators of an optical receiver.

Abstract: Producer/consumer mechanisms whereby the consumer issues a request to set up a monitor in a machine memory system. Incoming updates by a single or multiple producer(s) are recorded by the monitors and when an update to a subscribed location or region is observed, the memory system either records and counts the updates, or directly reflects the updates and forwards them to a single or multiple subscribed consumer(s).

Abstract: Energy-based diffusion models for transforming noisy inputs, the energy-based diffusion models including a denoiser model configured to transform a noisy input into a multiple candidate output predictions at each of a plurality of denoising iterations, and an energy-based model configured to transform the candidate output predictions at each denoising iteration into a single output prediction.

Abstract: Linear transformer models implementing a data-dependent gating mechanism and secondary chunking in the delta update to improve sequence modeling performance, wherein the gating mechanism is utilized with a decay term in the linear recurrence of the delta update process, enabling the linear transformer models to selectively forget features during modeling of long contexts.

Abstract: PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

Abstract: Mechanisms that enable particular model parameters and activations in artificial intelligence models to be stored in low precision, and that enable operations involved in inference computation to be performed using low-precision data paths, by leveraging fine-grained mixed-precision quantization. The mechanisms may utilize a combination of hardware and software logic to determine the model parameters and activations to maintain at higher precision and to identify with low latency the activation vectors to be retained in higher precision, as well as the corresponding mixed-precision data path design to facilitate efficient mixed-precision inference.

Abstract: Lithograph mask generation processes that apply optical lithography simulation on a mask image to generate a resist image, perform curvilinear design retargeting on the resist image, determine a gradient from the generated resist image and a configured target resist image, and apply morphological operators and the gradient to update the mask image.

Abstract: Animation systems including an expressive deformation model configured to transform expression settings, pose settings, and a template mesh into an animatable mesh, a first generator branch configured to transform identity controls for the animatable mesh into base Gaussian attributes, a second generator branch configured to transform detail controls for the animatable mesh into residual Gaussian attributes, the system configured to embed the base Gaussian attributes and residual Gaussian attributes in UV maps of the animatable mesh and to combine the UV maps and the animatable mesh to form an animatable Gaussian representation of an object to animate.

Abstract: Mechanisms to transform a multimodal hardware specification document into register-transfer level (RTL) code by configuring a large language model into multiple agents to transform the hardware specification document into a structured implementation plan comprising a sequence of hardware functions, configuring the large language model to apply progressive coding and prompt optimization to sequentially transform the hardware functions into low-level program code through a plurality of progressively lower-level code generation stages, and transforming the low-level program code of the hardware functions into the RTL code through a code optimizer and high-level synthesis tool.