Patents Assigned to NVIDIA Corp.
  • Semiconductor assembly
    Patent number: 11616019
    Abstract: A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 28, 2023
    Assignee: NVIDIA Corp.
    Inventors: Jacky Qiu, Martin Ding, Jerry Zhou, Minto Zheng
  • ADVERSARIAL SCENARIOS FOR SAFETY TESTING OF AUTONOMOUS VEHICLES
    Publication number: 20230079196
    Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 16, 2023
    Applicant: NVIDIA Corp.
    Inventors: Siva Kumar Sastry Hari, Iuri Frosio, Zahra Ghodsi, Anima Anandkumar, Timothy Tsai, Stephen W. Keckler, Alejandro Troccoli
  • Techniques to improve current regulator capability to protect the secured circuit from power side channel attack
    Patent number: 11594962
    Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 28, 2023
    Assignee: NVIDIA CORP.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Sanquan Song
  • CURRENT FLATTENING CIRCUIT FOR PROTECTION AGAINST POWER SIDE CHANNEL ATTACKS
    Publication number: 20230053487
    Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
    Type: Application
    Filed: October 13, 2022
    Publication date: February 23, 2023
    Applicant: NVIDIA Corp.
    Inventors: Nikola Nedovic, Sudhir Shrikantha Kudva
  • MEMORY INTERFACE WITH REDUCED ENERGY TRANSMIT MODE
    Publication number: 20230043152
    Abstract: PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.
    Type: Application
    Filed: February 9, 2022
    Publication date: February 9, 2023
    Applicant: NVIDIA Corp.
    Inventors: James Michael O'Connor, Donghyuk Lee
  • CONVERGENCE AMONG CONCURRENTLY EXECUTING THREADS
    Publication number: 20230038061
    Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 9, 2023
    Applicant: NVIDIA Corp.
    Inventors: Daniel Robert Johnson, Jack Choquette, Olivier Giroux, Michael Patrick McKeown, Mark Stephenson, Sana Damani
  • Deep learning based identification of difficult to test nodes
    Patent number: 11574097
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 7, 2023
    Assignee: NVIDIA CORP.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • Adversarial scenarios for safety testing of autonomous vehicles
    Patent number: 11550325
    Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 10, 2023
    Assignee: NVIDIA CORP.
    Inventors: Siva Kumar Sastry Hari, Iuri Frosio, Zahra Ghodsi, Anima Anandkumar, Timothy Tsai, Stephen W. Keckler, Alejandro Troccoli
  • AREA EFFICIENT MEMORY CELL READ DISTURB MITIGATION
    Publication number: 20220406371
    Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Andreas Jon Gotterba, Jesse Wang, Stefan P. Sywyk
  • Driver gaze tracking system for use in vehicles
    Patent number: 11506888
    Abstract: A gaze tracking system for use by the driver of a vehicle includes an opaque frame circumferentially enclosing a transparent field of view of the driver, light emitting diodes coupled to the opaque frame for emitting infrared light onto various regions of the driver's eye gazing through the transparent field of view, and diodes for sensing intensity of infrared light reflected off of various regions of the driver's eye.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 22, 2022
    Assignee: NVIDIA CORP.
    Inventors: Eric Whitmire, Kaan Aksit, Michael Stengel, Jan Kautz, David Luebke, Ben Boudaoud
  • Current flattening circuit for protection against power side channel attacks
    Patent number: 11507704
    Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 22, 2022
    Assignee: NVIDIA CORP.
    Inventors: Nikola Nedovic, Sudhir Shrikantha Kudva
  • CMOS SIGNALING FRONT END FOR EXTRA SHORT REACH LINKS
    Publication number: 20220353115
    Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Applicant: NVIDIA Corp.
    Inventors: Sanquan Song, John Poulton
  • Clock data recovery convergence in modulated partial response systems
    Patent number: 11477004
    Abstract: A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defend number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 18, 2022
    Assignee: NVIDIA CORP.
    Inventors: Pervez Mirza Aziz, Vishnu Balan, Viswanath Annampedu
  • Scalable light-weight protocols for wire-speed packet ordering
    Patent number: 11470394
    Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: October 11, 2022
    Assignee: NVIDIA CORP.
    Inventors: Hans Eberle, Larry Robert Dennison
  • Clock Data Recovery Convergence In Modulated Partial Response Systems
    Publication number: 20220311592
    Abstract: A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defined number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.
    Type: Application
    Filed: July 19, 2021
    Publication date: September 29, 2022
    Applicant: NVIDIA Corp.
    Inventors: Pervez Mirza Aziz, Vishnu Balan, Viswanath Annampedu
  • METHOD FOR ASSESSING THE QUALITY OF A ROBOTIC GRASP ON 3D DEFORMABLE OBJECTS
    Publication number: 20220297297
    Abstract: Candidate grasping models of a deformable object are applied to generate a simulation of a response of the deformable object to the grasping model. From the simulation, grasp performance metrics for stress, deformation controllability, and instability of the response to the grasping model are obtained, and the grasp performance metrics are correlated with robotic grasp features.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Applicant: NVIDIA Corp.
    Inventors: Isabella Huang, Yashraj Shyam Narang, Clemens Eppner, Balakumar Sundaralingam, Miles Macklin, Tucker Ryer Hermans, Dieter Fox
  • Reinforcement driven standard cell placement
    Publication number: 20220292335
    Abstract: An automatic standard cell layout generator that generates circuit layouts for an industry standard cell library on an advanced technology node leverages reinforcement learning (RL) to generate device placements in the layouts and also to fix design rule violations during routing. A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.
    Type: Application
    Filed: February 24, 2022
    Publication date: September 15, 2022
    Applicant: NVIDIA Corp.
    Inventor: Haoxing Ren
  • Convergence among concurrently executing threads
    Patent number: 11442795
    Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: September 13, 2022
    Assignee: NVIDIA Corp.
    Inventors: Daniel Robert Johnson, Jack Choquette, Oliver Giroux, Michael Patrick McKeown, Mark Stephenson, Sana Damani
  • Phase Locked Loop with Low Reference Spur
    Publication number: 20220286138
    Abstract: A calibration circuit including multiple charge pumps supplying a voltage controlled oscillator along different paths, one path being an integration path from a first one of the charge pumps to the voltage controlled oscillator, and one path being a proportional path from a second one of the charge pumps to the voltage controlled oscillator. A phase locked loop of the calibration circuit utilizes a switch capacitor circuit to reduce reference spur and improve the accuracy of clock edges for multi-phase calibration.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 8, 2022
    Applicant: NVIDIA Corp.
    Inventors: Chun-Ju Shen, Ying Wei, Vishnu Balan
  • Addressing cache slices in a last level cache
    Patent number: 11429534
    Abstract: A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: August 30, 2022
    Assignee: NVIDIA CORP.
    Inventors: Prakash Bangalore Prabhakar, James M. Van Dyke, Kun Fang