Patents Assigned to NVIDIA Corp.
  • Hardware-efficient PAM-3 encoder and decoder
    Patent number: 12135607
    Abstract: Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels and on an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on the error correction channel.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: November 5, 2024
    Assignee: NVIDIA Corp.
    Inventors: Gautam Bhatia, Sunil Sudhakaran, Kyutaeg Oh
  • Hardware-efficient PAM-3 encoder and decoder
    Patent number: 12132590
    Abstract: Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels, one or more auxiliary data channels, and an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on an error correction channel.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: October 29, 2024
    Assignee: NVIDIA, Corp.
    Inventor: Sunil Sudhakaran
  • Physically unclonable cell using dual-interlocking and error correction techniques
    Patent number: 12131800
    Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: October 29, 2024
    Assignee: NVIDIA Corp.
    Inventors: Mahmut Ersin Sinangil, Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray
  • Keeper-free volatile memory system
    Patent number: 12131775
    Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: October 29, 2024
    Assignee: NVIDIA Corp.
    Inventors: Lalit Gupta, Stefan P Sywyk, Andreas Jon Gotterba, Jesse Wang
  • ON DIE CURRENT SINK CIRCUIT FOR OVERSHOOT MITIGATION
    Publication number: 20240322559
    Abstract: An integrated circuit that includes multiple power rails with dummy loads configured on at least some of the power rails. The dummy loads are activated in response to a voltage overshoot condition on regions of the power rails at which the dummy loads are located. The dummy loads may be substituted for decoupling capacitors or other active cells at particular regions of the power rails.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Applicant: NVIDIA Corp.
    Inventors: Tezaswi Raja, Abhishek B Akkur, Jun Gu, Chengcheng Liu
  • System and methods for hardware-software cooperative pipeline error detection
    Patent number: 12099407
    Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: September 24, 2024
    Assignee: NVIDIA CORP.
    Inventors: Michael Sullivan, Siva Kumar Sastry Hari, Brian Matthew Zimmer, Timothy Tsai, Stephen W. Keckler
  • LOGIC CELL PLACEMENT MECHANISMS FOR IMPROVED CLOCK ON-CHIP VARIATION
    Publication number: 20240296274
    Abstract: Mechanisms to place flip-flops and other synchronous logic cells in a circuit layout in a clock on-chip variation-aware, predetermined order based on analysis of the clock gating, connectivity, and logic depth of the unplaced netlist. The resulting placements enable clock trees having a regular structure leading to improvements in clock on-chip variation, timing, and clock power.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 5, 2024
    Applicant: NVIDIA Corp.
    Inventors: Anand Kumar Rajaram, Erik Welty, David Lyndell Brown
  • VIA-BASED INDUCTOR COIL FOR INTEGRATED SILICON APPLICATIONS
    Publication number: 20240266106
    Abstract: Integrated inductors are formed by arranging multiple vias to bracket a volume of semiconductor substrate, where each via includes a top metal pad and a bottom metal pad. The vias are alternately connected by way of the top and bottom pads to form an end-to-end current loop along a length of the volume of semiconductor substrate.
    Type: Application
    Filed: February 7, 2023
    Publication date: August 8, 2024
    Applicant: NVIDIA Corp.
    Inventors: Joseph Minacapelli, Cong Gao
  • TRANSIENT CURRENT-MODE SIGNALING SCHEME FOR ON-CHIP INTERCONNECT FABRICS
    Publication number: 20240264625
    Abstract: Circuits that include one or more transmission lines to propagate a signal through a serially-arranged plurality of repeaters, and one or more control circuits to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise.
    Type: Application
    Filed: February 5, 2023
    Publication date: August 8, 2024
    Applicant: NVIDIA Corp.
    Inventors: Jiale Liang, Tezaswi Raja, Suhas Satheesh, Shalimar Rasheed, Gaurav Ajwani, Ram Kumar Ranjith Kumar, Miloni Mehta
  • Level-conversion circuits for signaling across voltage domains
    Patent number: 12047067
    Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: July 23, 2024
    Assignee: NVIDIA CORP.
    Inventors: Walker Joseph Turner, John Poulton, Sanquan Song
  • DIGITALLY CONTROLLED UNIFIED RECEIVER FOR MULTI-RANK SYSTEM
    Publication number: 20240235557
    Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply an analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 11, 2024
    Applicant: NVIDIA Corp.
    Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
  • Level-conversion circuits for signaling across voltage domains
    Patent number: 12009816
    Abstract: A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: June 11, 2024
    Assignee: NVIDIA CORP.
    Inventors: Walker Joseph Turner, John Poulton, Sanquan Song
  • ALIAS-FREE TAGGED ERROR CORRECTING CODES FOR MACHINE MEMORY OPERATIONS
    Publication number: 20240184670
    Abstract: Implicit Memory Tagging (IMT) mechanisms utilizing alias-free memory tags that enable hardware-assisted memory tagging without incurring storage overhead above those incurred by conventional tagging mechanisms, while providing enhanced data integrity and memory security. The IMT mechanisms enhance the utility of error correcting codes (ECCs) to test memory tags in addition to the traditional utility of ECCs for detecting and correcting data errors and enable a finer granularity of memory tagging than many conventional approaches.
    Type: Application
    Filed: October 11, 2023
    Publication date: June 6, 2024
    Applicant: NVIDIA Corp.
    Inventors: Michael B. Sullivan, Mohamed Tarek Bnziad Mohamed Hassan, Aamer Jaleel
  • Adaptive pixel sampling order for temporally dense rendering
    Patent number: 11997306
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: May 28, 2024
    Assignee: NVIDIA CORP.
    Inventors: Johan Pontus Andersson, Jim Nilsson, Tomas Guy Akenine-Möller
  • DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE
    Publication number: 20240161815
    Abstract: Multi-ported memories that include write peripheral logic configured to operate in a first voltage domain, read peripheral logic configured to operate in a second voltage domain, and at least one bit cell array, wherein the write peripheral logic and the read peripheral logic are disposed on opposite sides of the bit cell array and voltage domain crossings between the first voltage domain and the second voltage domain are localized in bit cells of the at least one bit cell array.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 16, 2024
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Jason Golbus, Jesse San-Jey Wang
  • PHYSICALLY UNCLONABLE CELL USING DUAL-INTERLOCKING AND ERROR CORRECTION TECHNIQUES
    Publication number: 20240161800
    Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Applicant: NVIDIA Corp.
    Inventors: Mahmut Ersin Sinangil, Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray
  • SCENE-AWARE SPEECH RECOGNITION USING VISION-LANGUAGE MODELS
    Publication number: 20240161749
    Abstract: A system to generate a latent space model of a scene or video and apply this latent space and candidate sentences formed from digital audio to a vision-language matching model to enhance the accuracy of speech-to-text conversion. A latent space embedding of the scene is generated in which similar features are represented in the space closer to one another. An embedding for the digital audio is also generated. The vision-language matching model utilizes the latent space embedding to enhance the accuracy of transcribing/interpreting the embedding of the digital audio.
    Type: Application
    Filed: June 22, 2023
    Publication date: May 16, 2024
    Applicant: NVIDIA Corp.
    Inventors: Gal Chechik, Shie Mannor
  • LOW-PRECISION FLOATING-POINT DATAPATH IN A COMPUTER PROCESSOR
    Publication number: 20240160406
    Abstract: Mechanisms to exploit the inherent resiliency of deep learning inference workloads to improve the energy efficiency of computer processors such as graphics processing units with these workloads. The mechanisms provide energy-accuracy tradeoffs in the computation of deep learning inference calculations via energy-efficient floating point data path micro-architectures with integer accumulation, and enhanced mechanisms for per-vector scaled quantization (VS-Quant) of floating-point arguments.
    Type: Application
    Filed: October 11, 2023
    Publication date: May 16, 2024
    Applicant: NVIDIA Corp.
    Inventors: Rangharajan Venkatesan, Reena Elangovan, Charbel Sakr, Brucek Kurdo Khailany, Ming Y Siu, Ilyas Elkin, Brent Ralph Boswell
  • Adversarial scenarios for safety testing of autonomous vehicles
    Patent number: 11977386
    Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA CORP.
    Inventors: Siva Kumar Sastry Hari, Iuri Frosio, Zahra Ghodsi, Anima Anandkumar, Timothy Tsai, Stephen W. Keckler, Alejandro Troccoli
  • Distributed global and local reference voltage generation
    Patent number: 11978496
    Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA CORP.
    Inventors: Jiwang Lee, Jaewon Lee, Po-Chien Chiang, Hsuche Nee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir