Abstract: A method for graphics processor clock scaling comprises the following steps. A percentage of idle-time is calculated, based upon an elapsed idle-time and an elapsed active time. A graphics processor clock rate is reduced if the percentage of idle time is higher than a high limit threshold. The graphics processor clock rate is increased if the percentage of idle time is lower than a low limit threshold.

Abstract: This disclosure describes an electronics device that effectively removes heat from the SoC, which increases its efficiency and extends its useful life by spreading heat in the thermally conductive plate before transferring it across the interface. Surface area is a significant factor in TIM thermal performance, so this increases the performance substantially when using the same type of TIM pad. This device allows the use of lower performance TIM pads that resolve the issues of high die pressure and non-resilient behavior of high thermal conductivity TIMs. Additionally, the device mechanically isolates the SoC from the heatsink, which reduces stress and provides improved thermal performance.

Abstract: A system, computer-readable medium, and method are provided for generating images based on adaptations of the human visual system. An input image is received, an effect provoking change is received, and an afterimage resulting from a cumulative effect of human visual adaptation is computed based on the effect provoking change and a per-photoreceptor type physiological adaptation of the human visual system. The computed afterimage may include a bleaching afterimage effect and/or a local adaptation afterimage effect. The computed afterimage is then accumulated into an output image for display.

Abstract: In embodiments of the invention, an apparatus may include a display comprising a plurality of pixels and a computer system coupled with the display and operable to instruct the display to display images. The apparatus may further include a microlens array located adjacent to the display and comprising a plurality of microlenses, wherein the microlens array is operable to produce a light field by altering light emitted by the display to simulate an object that is in focus to an observer while the display and the microlens array are located within a near-eye range of the observer.

Abstract: Embodiments are disclosed for a touch-based device and methods for operation thereof. One embodiment provides a touch-based device having a display with a plurality of pixels and a touch input sensor overlying the display. The touch input sensor has a plurality of touch regions, each of which overlie an associated set of the pixels. The touch-based device further comprises a display controller configured to update the pixels according to a schema during which pixels are updated during update periods. The touch-based device yet further comprises a touch controller configured to recognize selectively applied touch inputs at the plurality of touch regions. The touch controller and the display controller are synchronized such that, for a given touch region, touch input recognition is modified while the display controller is updating the set of pixels associated with that touch region.

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract: A method for processing a bitstream starts by shifting a bitstream of a first sample of a signal into a buffer. The buffer also holds bits of one or more additional bitstreams for one or more additional samples of the signal. Bits of a first half of the buffer are incrementally compared to corresponding bits of a second half of the buffer. Each bit of the first half of the buffer is compared to a corresponding bit of the second half of the buffer. A computation is performed on each bit of the first half of the buffer that is equal to a corresponding bit of the second half of the buffer. The results of the computations are summed to determine an output value for the first sample of the signal.

Abstract: An image capture application captures a sequence of images via a digital camera. The sequence of images may have undesirable levels of blurriness due to the motion of objects in the field of view of the digital camera or due to movement of the digital camera itself. A deblur engine within the image capture application generates image segments within one of the captured images, where a given image segment includes pixel values that move coherently between different images in the sequence. The deblur engine then deblurs each image segment based on the coherent motion of each different image segment and combines the resultant, deblurred image segments into a deblurred image. Advantageously, blurriness caused by the combined effects of moving objects and camera motion may be reduced, thereby improving the ability of a digital camera to provide high-quality images. As such, the user experience of digital photography may be enhanced.

Abstract: A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.

Abstract: One embodiment sets forth a method for efficiently determining memory resource dependencies between instructions included in a software application. For each instruction, a dependency analyzer uses overlapping search techniques to identify one or more overlaps between the memory elements included in the current instruction and the memory elements included in previous instructions. The dependency analyzer then maps objects included in the instructions to a set of partition elements wherein each partition element represents a set of memory elements that are functionally equivalent for dependency analysis. Subsequently, the dependency analyzer uses the set of partition elements to determine memory dependencies between the instructions at the memory element level.

Abstract: A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel.

Abstract: A method, computer readable medium, and system are disclosed for rendering images utilizing a foveated rendering algorithm with post-process filtering to enhance a contrast of the foveated image. The method includes the step of receiving a three-dimensional scene, rendering the 3D scene according to a foveated rendering algorithm to generate a foveated image, and filtering the foveated image using a contrast-enhancing filter to generate a filtered foveated image. The foveated rendering algorithm may incorporate aspects of coarse pixel shading, mipmapped texture maps, linear efficient anti-aliased normal maps, exponential variance shadow maps, and specular anti-aliasing techniques. The foveated rendering algorithm may also be combined with temporal anti-aliasing techniques to further reduce artifacts in the foveated image.

Abstract: A method comprises receiving an input signal at an input of a receiver and retrieving a data sample signal and an error sample signal from the input signal. The method also comprises applying an adaptive procedure to generate a feedback code using the data sample signal and the error sample signal for feeding back into a decision feedback equalization (DFE) module. Further, it comprises converting the feedback code into a corresponding voltage value and assigning the corresponding voltage value as a tap weight for the DFE module. Finally, it comprises generating an edge sample signal by applying DFE to the input signal using the DFE module, wherein the DFE is based on the tap weight.

Abstract: A method of entering a power conservation state comprises selecting and entering one of a plurality of low power states for the computer system in response to a detected system idle event. The plurality of low power states comprise a first low power state and a second low power state for the computer system. A memory of the computer system is self refreshed during the first low power state. A baseband module of the computer system remains powered, and the memory is accessible to the baseband module during the second low power state. The one low power state is selected depending upon baseband module activity. The method also includes exiting from the one of a plurality of low power states when a wake event is detected.

Abstract: A graphics processing subsystem and method for updating a voxel representation of a scene. One embodiment of the graphics processing subsystem includes: (1) a memory configured to store a voxel representation of a scene having first and second regions to be updated, and (2) a graphics processing unit (GPU) operable to: (2a) unify the first and second regions into a bounding region if a volume thereof does not exceed summed volumes of the first and second regions by more than a tolerance, and (2b) generate voxels for the bounding region and cause the voxels to be stored in the voxel representation.

Abstract: Stiffening is provided for an electronic package assembly having a substrate. A first electronic package, having a first function, is electromechanically fastened to a first surface of the substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the substrate first surface. A second electronic package, having a second function, is fastened to the first substrate surface with a second conductive interconnect array. At least a pair of the first array conductors is electrically coupled to at least a pair of the second array conductors for data/signal exchange and at least a component of the first electronic package interacts with at least a component of the second package. A metallic stiffener ring is disposed about an outer periphery of at least the central area of the substrate.

Abstract: A clock generator chip, a PCI Express port and a computing device control board are provided herein. In one embodiment the clock generator chip includes: (1) a clock generator configured to generate a reference clock signal for a component in response to a clock request from the component, (2) a reference clock pin configured to provide the reference clock signal and (3) a pair of sideband signal pins configured to receive and transmit sideband packets between the component and the clock generator chip.

Abstract: A system and method for performing computer algorithms. The system includes a graphics pipeline operable to perform graphics processing and an engine operable to perform at least one of a correlation determination and a convolution determination for the graphics pipeline. The graphics pipeline is further operable to execute general computing tasks. The engine comprises a plurality of functional units operable to be configured to perform at least one of the correlation determination and the convolution determination. In one embodiment, the engine is coupled to the graphics pipeline. The system further includes a configuration module operable to configure the engine to perform at least one of the correlation determination and the convolution determination.

Abstract: One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.

Abstract: A system, method, and computer program product are provided for shading using a dynamic object-space grid. An object defined by triangle primitives in a three-dimensional (3D) space that is specific to the object is received and an object-space shading grid is defined for a first triangle primitive of the triangle primitives based on coordinates of the first triangle primitive in the 3D space. A shader program is executed by a processing pipeline to compute a shaded value at a point on the object-space shading grid for the first triangle primitive.