Patents Assigned to NVidia
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Patent number: 9754561Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.Type: GrantFiled: October 4, 2013Date of Patent: September 5, 2017Assignee: NVIDIA CORPORATIONInventors: Jonathan Dunaisky, Henry Packard Moreton, Jeffrey A. Bolz, Yury Y. Uralsky, James Leroy Deming, Rui M. Bastos, Patrick R. Brown, Amanpreet Grewal, Christian Amsinck, Poornachandra Rao, Jerome F. Duluk, Jr., Andrew J. Tao
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Patent number: 9756222Abstract: Embodiments of the present invention are operable to perform automatic white balancing operations on images captured by a camera system through the use of weights derived through crowdsourcing procedures. Embodiments of the present invention use crowdsourced weight data resident on the camera system in combination with sampled image data of a captured image to determine a likely illuminant source. When performing automatic white balancing operations on the captured image, embodiments of the present invention may also compute a confidence score which may present the user with a choice to either use the likely illuminant determined using the crowdsourced weights or the camera system's default or normal automatic white balancing correction algorithm.Type: GrantFiled: June 26, 2013Date of Patent: September 5, 2017Assignee: Nvidia CorporationInventors: Brian Cabral, Ricardo Motta, Mitchell Harwell
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Publication number: 20170249254Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.Type: ApplicationFiled: October 16, 2013Publication date: August 31, 2017Applicant: NVIDIA CorporationInventors: Jerome F. DULUK, JR., Cameron BUSCHARDT, Sherry CHEUNG, James Leroy DEMING, Samuel H. DUNCAN, Lucien DUNNING, Robert GEORGE, Arvind GOPALAKRISHNAN, Mark HAIRGROVE, Chenghuan JIA, John MASHEY
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Patent number: 9746969Abstract: A flat panel electronic device is presented. The flat panel electronic device comprises an actuating apparatus, a supporting apparatus and a control apparatus. The actuating apparatus is configured to generate a first actuating signal. The supporting apparatus has an extending position and an initial position, wherein the supporting apparatus is configured to support at least a portion of the flat panel electronic device to a predetermined height when the supporting apparatus is in the extending position. The control apparatus is configured to control the movement of the supporting apparatus in response to the first actuating signal. In addition, the supporting apparatus can also have an additional function for adjusting the angle of the display panel of the flat panel electronic device with respect to the user, so as to improve the comfort level for watching.Type: GrantFiled: April 17, 2013Date of Patent: August 29, 2017Assignee: NVIDIA CORPORATIONInventor: Mingyi Yu
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Patent number: 9747718Abstract: A system, method, and computer program product are provided for performing object-space shading. A primitive defined by vertices in three-dimensional (3D) space that is specific to an object defined by at least the primitive is received and a shading sample rate is computed for the primitive based on a screen-space derivative of coordinates of a pixel fragment transformed into the 3D space. A shader program is executed by a processing pipeline to compute shaded attributes for the primitive according to the computed shading sample rate.Type: GrantFiled: March 11, 2015Date of Patent: August 29, 2017Assignee: NVIDIA CorporationInventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, Jr., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
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Patent number: 9747107Abstract: A system and method for compiling or runtime executing a fork-join data parallel program with function calls. In one embodiment, the system includes: (1) a partitioner operable to partition groups into a master group and at least one worker group and (2) a thread designator associated with the partitioner and operable to designate only one thread from the master group for execution and all threads in the at least one worker group for execution.Type: GrantFiled: December 21, 2012Date of Patent: August 29, 2017Assignee: Nvidia CorporationInventors: Yuan Lin, Gautam Chakrabarti, Jaydeep Marathe, Okwan Kwon, Amit Sabne
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Patent number: 9747527Abstract: In one embodiment of the present invention, a graphics processing unit (GPU) is configured to detect an object in an image using a random forest classifier that includes multiple, identically structured decision trees. Notably, the application of each of the decision trees is independent of the application of the other decision trees. In operation, the GPU partitions the image into subsets of pixels, and associates an execution thread with each of the pixels in the subset of pixels. The GPU then causes each of the execution threads to apply the random forest classifier to the associated pixel, thereby determining a likelihood that the pixel corresponds to the object. Advantageously, such a distributed approach to object detection more fully leverages the parallel architecture of the PPU than conventional approaches. In particular, the PPU performs object detection more efficiently using the random forest classifier than using a cascaded classifier.Type: GrantFiled: September 17, 2013Date of Patent: August 29, 2017Assignee: NVIDIA CorporationInventors: Mateusz Jerzy Baranowski, Shalini Gupta, Elif Albuz
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Patent number: 9746954Abstract: A touch-screen input/output device including a touch sensor, a display, a display control module, a touch sensor control module and a synchronizer module. The touch sensor is overlaid on a display. The display control module is communicatively coupled to the display and converts video data into a serial bit stream video display signal include one or more blanking intervals. The touch sensor control module is communicatively coupled to the touch sensor and determines touch events and location of the touch event on the touch sensor during one or more touch sensor scan cycles. The synchronizer module is communicatively coupled between the display control module and the touch sensor control module, and interleaves the one or more touch sensor scan cycles with the one or more blanking intervals of the video display signal.Type: GrantFiled: August 11, 2015Date of Patent: August 29, 2017Assignee: NVIDIA CORPORATIONInventors: David Wyatt, Arman Toorians
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Patent number: 9747661Abstract: A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases.Type: GrantFiled: October 24, 2016Date of Patent: August 29, 2017Assignee: NVIDIA CorporationInventors: Eric Brian Lum, Henry Packard Moreton, Kyle Perry Roden, Walter Robert Steiner, Ziyad Sami Hakura
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Patent number: 9740553Abstract: Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.Type: GrantFiled: November 14, 2012Date of Patent: August 22, 2017Assignee: NVIDIA CORPORATIONInventors: Bruce Holmer, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell D. Boggs, Magnus Ekman
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Patent number: 9742869Abstract: A request management subsystem is configured to establish service classes for clients that issue requests for a shared resource on a computer system. The subsystem also is configured to determine the state of the system with respect to bandwidth, current latency, frequency and voltage levels, among other characteristics. Further, the subsystem is configured to evaluate the requirements of each client with respect to latency sensitivity and required bandwidth, among other characteristics. Finally, the subsystem is configured to schedule access to shared resources, based on the priority class of each client, the demands of the application, and the state of the system. With this approach, the subsystem may enable all clients to perform optimally or, alternatively, may cause all clients to experience an equal reduction in performance.Type: GrantFiled: December 9, 2013Date of Patent: August 22, 2017Assignee: NVIDIA CorporationInventors: Evgeny Bolotin, Zvi Guz, Adwait Jog, Stephen William Keckler, Michael Allen Parker
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Patent number: 9741098Abstract: A digital camera includes an image optimization engine configured to generate an optimized image based on a raw image captured by the digital camera. The image optimization engine implements one or more machine learning engines in order to select rendering algorithms and rendering algorithm arguments that may then be used to render the raw image.Type: GrantFiled: October 12, 2012Date of Patent: August 22, 2017Assignee: NVIDIA CorporationInventor: Michael Brian Cox
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Patent number: 9742396Abstract: Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level.Type: GrantFiled: January 13, 2015Date of Patent: August 22, 2017Assignee: NVIDIA CorporationInventor: Alan Li
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Patent number: 9740046Abstract: A system and method are provided for displaying a lower power user interface on an liquid crystal display (LCD) panel using localized backlight control. The method includes the step of identifying a subset of light emitting elements included in a backlight for the LCD panel, where the backlight includes a plurality of light emitting elements. The subset of light emitting elements consumes less power when operated individually or in combination with other subsets of light emitting elements than the total backlight with all light emitting elements simultaneously active. The method also includes the steps of activating the subset of light emitting elements to at least partially illuminate the LCD panel while at least one light emitting element is not activated, adjusting an image for a user interface based on a compensation map corresponding to the subset of light emitting elements, and displaying the adjusted image on the LCD panel.Type: GrantFiled: January 7, 2014Date of Patent: August 22, 2017Assignee: NVIDIA CorporationInventor: David Wyatt
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Publication number: 20170237997Abstract: A method for performing image decompression. The method includes identifying a pixel in an image, wherein the image comprises a plurality of tiles including color data that is displayed by a plurality of pixels, wherein each tile is associated with a base value, a delta value, and a plurality of indices. One or more tiles associated with the pixel are identified. An interpolated base is determined by interpolating decompressed bases of the one or more tiles. An interpolated delta is determined by interpolating deltas of the one or more tiles. An index is determined for the pixel. A color value is determined for the pixel based on the interpolated base, interpolated delta, and the index.Type: ApplicationFiled: February 23, 2012Publication date: August 17, 2017Applicant: NVIDIA CORPORATIONInventors: Walter E. Donovan, Tyson J. Bergland
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Patent number: 9734548Abstract: One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.Type: GrantFiled: August 28, 2013Date of Patent: August 15, 2017Assignee: NVIDIA CorporationInventors: Ziyad S. Hakura, Rouslan Dimitrov, Emmett M. Kilgariff, Andrei Khodakovsky
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Patent number: 9734545Abstract: One embodiment of the present invention sets forth a technique for executing a software method within a graphics processing unit (GPU) that minimizes the number of clock cycles during which the graphics engine is idled. The function of the software method is performed by a firmware method that is executed by a processor within the GPU. The firmware method is executed to access and optionally update the state stored in the GPU. Unlike execution of a conventional software method, execution of the firmware method does not require an exchange of information between a CPU and the GPU. Therefore, the CPU is not interrupted and throughput of the CPU is not reduced.Type: GrantFiled: October 7, 2010Date of Patent: August 15, 2017Assignee: NVIDIA CorporationInventors: Jerome F. Duluk, Jr., John Christopher Cook, Fred Gruner, Gregory Scott Palmer
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Patent number: 9734546Abstract: A computer system includes an operating system having a kernel and configured to launch a plurality of computing processes. The system also includes a plurality of graphics processing units (GPUs), a front-end driver module, and a plurality of back-end driver modules. The GPUs are configured to execute instructions on behalf of the computing processes subject to a GPU service request. The front-end driver module is loaded into the kernel and configured to receive the GPU service request from one of the computing processes. Each back-end driver module is associated with one or more of the GPUs and configured to receive the GPU service request from the front-end driver module and pass the GPU service request to an associated GPU.Type: GrantFiled: October 3, 2013Date of Patent: August 15, 2017Assignee: NVIDIA CorporationInventors: Kirti Wankhede, Andrew Currid, Surath Raj Mitra, Chenghuan Jia
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Patent number: 9728481Abstract: An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.Type: GrantFiled: September 7, 2011Date of Patent: August 8, 2017Assignee: NVIDIA CorporationInventors: Abraham F. Yee, Joe Greco, Jun Zhai, Joseph Minacapelli, John Y. Chen
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Patent number: 9727463Abstract: A method of caching data in the memory of electronic processor units including compiling, in a first processor configured to perform data-parallel computation, a set of asymmetric coherent caching rules. The set of rules configure the first processor to be: inoperable to cache, in a second level memory cache of the first electronic processor unit, data whose home location is in a final memory store of a second electronic processor unit; operable to cache, in the second level memory cache of the first electronic processor unit, the data whose home location is in a final memory store of the first electronic processor unit; and operable to cache, in a first level memory cache of the first electronic processor unit, the data, regardless of a home location of the data.Type: GrantFiled: October 14, 2015Date of Patent: August 8, 2017Assignee: Nvidia CorporationInventor: John Danskin