Abstract: A cooling subsystem is provided for dissipating heat from processor. The cooling subsystem includes a heat sink comprising an upper portion having a plurality of fins formed therein and a base portion fixed to the upper portion to form a vapor chamber in an enclosed volume between the upper portion and the base portion.

Abstract: A system and method for executing sequential code in the context of a single-instruction, multiple-thread (SIMT) processor. In one embodiment, the system includes: (1) a pipeline control unit operable to create a group of counterpart threads of the sequential code, one of the counterpart threads being a master thread, remaining ones of the counterpart threads being slave threads and (2) lanes operable to: (2a) execute certain instructions of the sequential code only in the master thread, corresponding instructions in the slave threads being predicated upon the certain instructions and (2b) broadcast branch conditions in the master thread to the slave threads.

Abstract: A system and method for compressing stencil data attendant to rendering an image. In one embodiment, the method includes: (1) selecting a base stencil value for a particular group, (2) selecting a single-bit delta value for each sample in the particular group and (3) storing the stencil base value and the delta values in a frame buffer.

Abstract: A method includes scanning, through a processor of a data processing device communicatively coupled to a memory, display data to be rendered on a display unit communicatively coupled to the data processing device for boundaries of one or more virtual object(s) therein. The method also includes rendering, through the processor, a portion of the display data outside the boundaries of the one or more virtual object(s) at a reduced level compared to a portion of the display data within the boundaries on the display unit.

Abstract: One embodiment of the present disclosure sets forth an enhanced way for GPUs to queue new computational tasks into a task metadata descriptor queue (TMDQ). Specifically, memory for context data is pre-allocated when a new TMDQ is created. A new TMDQ may be integrated with an existing TMDQ, where computational tasks within that TMDQ include task from each of the original TMDQs. A scheduling operation is executed on completion of each computational task in order to preserve sequential execution of tasks without the use of atomic locking operations. One advantage of the disclosed technique is that GPUs are enabled to queue computational tasks within TMDQs, and also create an arbitrary number of new TMDQs to any arbitrary nesting level, without intervention by the CPU. Processing efficiency is enhanced where the GPU does not wait while the CPU creates and queues tasks.

Abstract: A device compiler and linker within a parallel processing unit (PPU) is configured to optimize program code of a co-processor enabled application by rematerializing a subset of live-in variables for a particular block in a control flow graph generated for that program code. The device compiler and linker identifies the block of the control flow graph that has the greatest number of live-in variables, then selects a subset of the live-in variables associated with the identified block for which rematerializing confers the greatest estimated profitability. The profitability of rematerializing a given subset of live-in variables is determined based on the number of live-in variables reduced, the cost of rematerialization, and the potential risk of rematerialization.

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Abstract: A method of generating an image. The method includes simulating a presence of at least one light source within a virtualized three dimensional space. Within the virtualized three dimensional space, a light sensing plane is defined. The light sensing plane includes a matrix of a number of pixels to be displayed on a display screen. The method further includes using a light transport procedure, computing a gradient value for each pixel of the matrix to produce a number of gradient values. The gradient computation involves selecting a plurality of light path pairs that contribute to a pixel wherein the selection is biased towards selection of more light paths that pass through pixels having larger gradient values. The plurality of gradient values are converted to a plurality of light intensity values which represent the image.

Abstract: A system, method, and computer program product are provided for implementing anti-aliasing operations using a programmable sample pattern table. The method includes the steps of receiving an instruction that causes one or more values to be stored in one or more corresponding entries of the programmable sample pattern table and performing an anti-aliasing operation based on at least one value stored in the programmable sample pattern table. At least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels.

Abstract: One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle. The smaller tasks do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second cycle are balanced and make full use of resources. Therefore, the performance of the tessellation and geometry shaders is improved.

Abstract: Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the request accesses a location in DRAM where no virtual bank manager includes parameters for the corresponding DRAM page, then a virtual bank manager is allocated to the physical bank associated with the DRAM page. The bank manager is initialized to include parameters needed by the DRAM controller to access the DRAM page. The memory access request is then processed using the parameters associated with the virtual bank manager. One advantage of the disclosed technique is that the banks of a DRAM module are controlled with fewer bank managers than in previous DRAM controller designs. As a result, less surface area on the DRAM controller circuit is dedicated to bank managers.

Abstract: A system, method, and computer program product are provided for accessing multi-sample surfaces. A multi-sample store instruction that specifies data for a single sample of a multi-sample pixel and a sample mask is received and the data for the single sample is stored to each sample of the multi-sample pixel that is enabled according to the sample mask. A multi-sample load instruction that specifies a multi-sample pixel is received, and, in response to executing the multi-sample load instruction, data for one sample of the multi-sample pixel is received. A determination is made that the data for the one sample of the multi-sample pixel represents multi-sample pixel data for at least one additional sample of the multi-sample pixel.

Abstract: One embodiment of the present invention sets forth a computer-implemented method for altering migration rules for a unified virtual memory system. The method includes detecting that a migration rule trigger has been satisfied. The method also includes identifying a migration rule action that is associated with the migration rule trigger. The method further includes executing the migration rule action. Other embodiments of the present invention include a computer-readable medium, a computing device, and a unified virtual memory subsystem. One advantage of the disclosed approach is that various settings of the unified virtual memory system may be modified during program execution. This ability to alter the settings allows for an application to vary the manner in which memory pages are migrated and otherwise manipulated, which provides the application the ability to optimize the unified virtual memory system for efficient execution.

Abstract: Systems and methods for throttling GPU execution performance to avoid surges in DI/DT. A processor includes one or more execution units coupled to a scheduling unit configured to select instructions for execution by the one or more execution units. The execution units may be connected to one or more decoupling capacitors that store power for the circuits of the execution units. The scheduling unit is configured to throttle the instruction issue rate of the execution units based on a moving average issue rate over a large number of scheduling periods. The number of instructions issued during the current scheduling period is less than or equal to a throttling rate maintained by the scheduling unit that is greater than or equal to a minimum throttling issue rate. The throttling rate is set equal to the moving average plus an offset value at the end of each scheduling period.

Abstract: A system, method, and computer program product are provided for constructing a hierarchical acceleration data structure that supports ray tracing of motion blur. In use, scene description data associated with an image to be generated is received. Additionally, a hierarchical acceleration data structure for performing ray tracing on the scene description data is constructed, where the hierarchical acceleration data structure supports ray tracing of motion blur.

Abstract: One embodiment of the present invention sets forth a technique for reducing flicker in image frames captured with a rolling shutter. A flicker detection and correction engine selects a first channel from a first image frame for processing. The flicker detection and correction engine subtracts each pixel value in the first channel from a corresponding pixel value in a prior image frame to generate a difference image frame. The flicker detection and correction engine identifies a first alternating current (AC) component based on a discrete cosine transform (DCT) associated with the difference image frame. The flicker detection and correction engine reduces flicker that is present in the first image frame based on the first AC component. One advantage of the disclosed techniques is that the flicker resulting from fluctuating light sources is correctly detected and reduced or eliminated irrespective of the frequency of the fluctuating light source.

Abstract: Multi-level prediction mode encoding type decision methods and systems are presented. In one embodiment, an indication of a prediction mode level is received and encoding is performed in accordance with said prediction mode level. The indication of said prediction mode level is programmable and can be set at different levels. The prediction mode level can be associated with a programmable encoding type decision point (e.g., early, intermediate, late, etc.). The encoding process includes deciding upon an I-type or P-type encoding. In one embodiment, a multi-stage encoding type method is also implemented in intra-prediction related search and inter-prediction related search and respective corresponding prediction operations are performed, wherein at least a portion of the intra-prediction related search and the inter-prediction related search are performed in parallel.

Abstract: A system, method, and computer program product are provided for simulating light transport. In operation, a distribution function is decomposed utilizing a technique for sampling from a probability distribution (e.g. the Alias Method, etc.). Additionally, light transport associated with at least one scene is simulated utilizing information associated with the decomposed distribution function.

Abstract: In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

Abstract: A mobile computing device comprising a display panel and a home button, the display panel being disposed on the exterior front surface and the home button being disposed on the exterior back surface of the mobile computing device. The front surface may be free of any additional user Input/Output devices apart from the display panel. The mobile computing device may further comprise an accelerometer and a phone circuit. Upon detection that the display panel faces away from a user during a phone call, displayed information on the display panel may be concealed automatically. The accelerometer may be also operable to detect shaking motions on the mobile computing device as a user command to turn on or turn off the display panel.