Abstract: A system and method for correcting image data. Embodiments of the present invention provide calibration and image correction to overcome various lens effects including lens shading and lens imperfections. In one embodiment, the correction of image data is performed via utilization of a spline surface (e.g., Bezier surface). The use of spline surfaces facilitates efficient hardware implementation. The image correction may be performed on a per channel and illumination type basis. In another embodiment, the present invention provides a method for determine a spline surface to be used for calibrating an image signal processor to be used in correcting image data.

Abstract: A system, method, and computer program product for optimizing thread stack memory allocation is disclosed. The method includes the steps of receiving source code for a program, translating the source code into an intermediate representation, analyzing the intermediate representation to identify at least two objects that could use a first allocated memory space in a thread stack memory, and modifying the intermediate representation by replacing references to a first object of the at least two objects with a reference to a second object of the at least two objects.

Abstract: One embodiment of the present invention sets forth a graphics subsystem. The graphics subsystem includes a first tiling unit associated with a first set of raster tiles and a crossbar unit. The crossbar unit is configured to transmit a first set of primitives to the first tiling unit and to transmit a first cache invalidate command to the first tiling unit. The first tiling unit is configured to determine that a second bounding box associated with primitives included in the first set of primitives overlaps a first cache tile and that the first bounding box overlaps the first cache tile. The first tiling unit is further configured to transmit the primitives and the first cache invalidate command to a first screen-space pipeline associated with the first tiling unit for processing. The screen-space pipeline processes the cache invalidate command to invalidate cache lines specified by the cache invalidate command.

Abstract: A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.

Abstract: When a computing system is running at a lower clock rate, in response to an event that triggers the computing system to increase the clock rate, a list of threads pending execution by the computing system is accessed. The list includes a thread that, when executed, causes the clock rate to increase. That thread is selected and executed before any other thread in the list is executed.

Abstract: A method for sub-pixel texture mapping and filtering is provided. The method includes the steps of: dividing an area on a source image into a red (R) sub-area, a green (G) sub-area, and a blue (B) sub-area, where the area on the source image is corresponding to a pixel of a destination image presented by a display device; sampling the R sub-area to obtain a R color value, sampling the G sub-area to obtain a G color value, and sampling the B sub-area to obtain a B color value; and rendering R, G, B color components of the pixel of the destination image according to the R color value, the G color value, and the B color value.

Abstract: A tessellation pipeline includes an alpha phase and a beta phase. The alpha phase includes pre-tessellation processing stages, while the beta phase includes post-tessellation processing stages. A processing unit configured to implement a processing stage in the alpha phase stores input graphics data within a buffer and then copies over that buffer with output graphics data, thereby conserving memory resources. The processing unit may also copy output graphics data directly to a level 2 (L2) cache for beta phase processing by other tessellation pipelines, thereby avoiding the need for fixed function copy-out hardware.

Abstract: A system and method are described for compressing image data using a combination of compression methods. Compression method combinations are provided to compress image data of a particular frame buffer format and antialiasing mode. Each method in the compression method combination is tried in turn to compress the image data in a tile. The best method that succeeded in compressing the image data is encoded in the compression bit state associated with the tile. Together, the compression bits, the compression method combination, and the frame buffer format provide sufficient information to decompress a tile.

Abstract: An approach is provided for performing back-end operations for camera control. In one example, a method includes the following: receiving a user edit via a user interface device that displays an interpretation of a scene at which a camera lens of the camera is pointing, wherein the user edit is based on user input that is associated with a selection region on the user interface device; generating an edits mask based on one or more matching image patches, which are based on the user edit and a high dynamic range (HDR) image generated by the camera; performing one or more tone mapping operations based on the edits mask and the HDR image in order to generate a tone mapped HDR image; and performing one or more metering operations based on the edits mask and the tone mapped HDR image in order to generate metering parameters for frame capturing operations.

Abstract: This disclosure is directed to systems and methods for sorting data in which pre-sorting operations are performed on keys prior to those keys being reordered within memory. One example method includes generating, for each of a plurality of keys, an associated modified key. This operation is an example pre-sorting operation that occurs prior to any reordering of the keys. Once the modified keys are generated, the modified keys and/or associated information are processed in order to change the ordering of the keys in memory.

Abstract: A system and method for implementing memory overlays for portable pointer variables. The method includes providing a program executable by a heterogeneous processing system comprising a plurality of a processors running a plurality of instruction set architectures (ISAs). The method also includes providing a plurality of processor specific functions associated with a function pointer in the program. The method includes executing the program by a first processor. The method includes dereferencing the function pointer by mapping the function pointer to a corresponding processor specific feature based on which processor in the plurality of processors is executing the program.

Abstract: A first transceiver is configured to transmit a first data signal to a second transceiver across a communication link. The second transceiver maintains clock data recovery (CDR) lock with the first signal by adjusting a sampling clock configured to sample the first data signal. When the communication link reverses directions, the second transceiver is configured to transmit a second data signal to the first transceiver with the phase of that second data signal adjusted based on the adjustments made to the sampling clock.

Abstract: One embodiment of the present invention sets forth a technique for tracking and filtering state change methods provided to a graphics pipeline. State shadow circuitry at the start of the graphics pipeline may be configured in different modes. A track mode is used to capture the current state by storing state change methods that are transmitted to the graphics pipeline. A passthrough mode is used to provide different state data to the graphics pipeline without updating the current state stored in the state shadow circuitry. A replay mode is used to restore the current state to the graphics pipeline using the state shadow circuitry. Additionally, the state shadow circuitry may also be configured to filter the state change methods that are transmitted to graphics pipeline by removing redundant state change methods.

Abstract: Embodiments of the present invention are directed to a novel approach for realistically modeling sub-surface scattering effects in three-dimensional objects of graphically rendered images. In an embodiment, an indirection map is generated for an image by analyzing the triangle mesh of one or more three-dimensional objects in the image and identifying pairs of edges between adjacent triangles in the mesh that have the same spatial locations in the three-dimensional representations, but which have different locations in the texture map. For each of these edges, the opposite triangle in each pair is projected into their corresponding edge's two-dimensional space. This allows samples which cross a seam in the two dimensional representation that would otherwise sample out into invalid data to be redirected to the spatially correct region of the texture and generate consistent results with non-seam areas.

Abstract: Sequential fetch requests from a set of fetch requests are combined into longer coalesced requests that match the width of a system memory interface in order to improve memory access efficiency for reading the data specified by the fetch requests. The fetch requests may be of different classes and each data class is coalesced separately, even when intervening fetch requests are of a different class. Data read from memory is ordered according to the order of the set of fetch requests to produce an instruction stream that includes the fetch requests for the different classes.

Abstract: A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, where each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, where each partition receives a respective one of the plurality of second clock signals and where the plurality of second clock signals are staggered where each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency.

Abstract: A system and method are provided for regulating a voltage level at a load. The method configures a current control mechanism to generate a current through a first inductor and a second inductor that are coupled in series and configures a voltage control mechanism to provide a portion of the current to regulate the voltage level. The second inductor isolates the load from a parasitic capacitance of the current control mechanism. An electric power conversion device for regulating the voltage level at the load comprises the current control mechanism that is coupled to an electric power source and configured to generate a current through the first inductor and the second inductor that are coupled in series and the voltage control mechanism that is coupled to the second inductor and configured to provide a portion of the current to regulate the voltage level.

Abstract: One embodiment sets forth a method for transforming 3-D images into 2-D rendered images using render target sample masks. A software application creates multiple render targets associated with a surface. For each render target, the software application also creates an associated render target sample mask configured to select one or more samples included in each pixel. Within the graphics pipeline, a pixel shader processes each pixel individually and outputs multiple render target-specific color values. For each render target, a ROP unit uses the associated render target sample mask to select covered samples included in the pixel. Subsequently, the ROP unit uses the render target-specific color value to update the selected samples in the render target, thereby achieving sample-level color granularity.

Abstract: In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.

Abstract: Power management techniques for a Universal Serial Bus (USB) include determining an idle period on one or more USB ports by a main controller circuit of a USB host controller. The main controller circuit signals a suspend to a Power Management Controller (PMC) sub-circuit of the USB host controller, in response to the determined idle period. The PMC sub-circuit stores one or more operating parameters of the one or more USB ports in response to the suspend signal. The PMC sub-circuit also maintains the idle state on the one or more USB ports in response to the suspend signal. Thereafter, the main controller circuit is placed in a low energy state while the PMC sub-circuit maintains the idle state.