Patents Assigned to NVidia
  • Video decoding error concealment techniques
    Patent number: 9386326
    Abstract: Techniques for synchronizing error concealment during video decoding include determining a decoding error. A recovery point within a current frame is determined for each decoding error. The determined recovery point may be the start of the next good slice of a frame after the current frame containing the error. The number of macroblock to be concealed is also determined. The determined number of macroblocks from the recovery point may then be concealed in hardware or software. The techniques for concealing errors may also include determining available macroblocks for use in concealing the error. The techniques for concealing errors may further include selecting a given concealment mode.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: July 5, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Krishna Kishor Noru, Nitin Jadon, Shu-Jen Fang, Prahlad Venkatapuram, Visalakshi Vaduganathan
  • Custom chaining stubs for instruction code translation
    Patent number: 9384001
    Abstract: A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: July 5, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Ben Hertzberg, Nathan Tuck
  • Decoupling capacitors for interposers
    Patent number: 9379202
    Abstract: Embodiments of the invention generally relate to interposers for packaging integrated circuits. The interposers include capacitive devices for reducing signal noise and leakage between adjacent integrated circuits coupled to the interposers. The capacitive devices are formed from doped semiconductor layers. In one embodiment, an interposer includes a substrate having doped regions of opposing conductivities. First and second oxide layers are disposed over the doped regions. A first interconnect disposed in the second oxide layer is electrically coupled to a doped region of a first conductivity, and a second interconnect disposed in the second oxide is electrically coupled to a doped region of a second conductivity. Additional capacitive devices utilizing doped semiconductor layers are also disclosed.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: June 28, 2016
    Assignee: NVIDIA CORPORATION
    Inventor: Abraham F. Yee
  • Per-channel image intensity correction
    Patent number: 9379156
    Abstract: Techniques for per-channel image intensity correction includes linear interpolation of each channel of spectral data to generate corrected spectral data.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: June 28, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Brian Cabral, Hu He, Elena Ing, Sohei Takemoto
  • System for reducing peak power during scan shift at the global level for scan based tests
    Patent number: 9377510
    Abstract: A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 28, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Milind Sonawane, Satya Puvvada, Amit Sanghani
  • System, method, and computer program product for low latency scheduling and launch of memory defined tasks
    Patent number: 9378139
    Abstract: A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task metadata data structure to be stored in a memory associated with a processor, transmitting the task metadata data structure to a scheduling unit of the processor, storing the task metadata data structure in a cache unit included in the scheduling unit, and copying the task metadata data structure from the cache unit to the memory.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: June 28, 2016
    Assignee: NVIDIA Corporation
    Inventors: Scott Ricketts, Brian Scott Pharris, Nicholas Wang, Luke David Durant, Philip Alexander Cuadra, Jerome F. Duluk, Jr.
  • Method and system for changing bus direction in memory systems
    Patent number: 9378169
    Abstract: A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: June 28, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Ambuj Kumar, Brian Keith Langendorf, Sharath Raghava, Tony Yuhsiang Cheng
  • Method and system for testing a memory
    Patent number: 9373416
    Abstract: A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be tested of the memory is set to a fixed value. Current test data is written into memory unit(s) of the memory which the set address bit(s) correspond(s) to. Current read back data is read from the memory unit(s) which the set address bit(s) correspond(s) to. The current test data is compared with the current read back data. It is judged whether there is any signal integrity problem in unset address bit(s) of the memory according to the comparison result of the current test data and the current read back data, in order to determine fault address bit(s). The method and system for testing a memory provided by the present invention may determine fault address bit(s) of the memory simply and quickly.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: June 21, 2016
    Assignee: NVIDIA Corporation
    Inventors: Fei Wang, Yu Zhao, Xiang Sun
  • Substrate build up layer to achieve both finer design rule and better package coplanarity
    Patent number: 9368439
    Abstract: Embodiments of the invention generally relate to package substrates for integrated circuits. The package substrates each include a core having electrically conductive vias therethrough. Build-up layers formed from dielectric materials having different compositions are disposed around the core and include interconnects formed therein for facilitating electrical connections between integrated circuits coupled to the package substrate. The dielectric materials are selected to allow finer interconnect geometries where desired, and to increase the rigidity, and thus planarity, of the package substrate. Exemplary dielectric materials include pre-impregnated composite fibers for increasing the rigidity of a package substrate, and Ajinomoto Build-up Film for allowing the formation finer interconnect geometries.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: June 14, 2016
    Assignee: NVIDIA Corporation
    Inventors: Leilei Zhang, Zuhair Bokharey
  • Wideband antenna and an electronic device including the same
    Patent number: 9368862
    Abstract: Provided is an antenna. The antenna, in one embodiment, includes a feed element having a first feed element end and a second feed element end, the first feed element end configured to electrically connect to a positive terminal of a transmission line. The antenna, in this embodiment, further includes a ground element having a first ground element end and a second ground element end, the first ground element end configured to electrically connect to a negative terminal of the transmission line. In this particular embodiment, the first ground element end is located proximate and inside the first feed element end, and the second ground element end is located proximate and outside the second feed element end.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: June 14, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Sung Hoon Oh, Joselito Gavilan, Warren Lee
  • Computing system and method for representing volumetric data for a scene
    Patent number: 9367946
    Abstract: A computing system and method for representing volumetric data for a scene. One embodiment of the computing system includes: (1) a memory configured to store a three-dimensional (3D) clipmap data structure having at least one clip level and at least one mip level, and (2) a processor configured to generate voxelized data for a scene and cause the voxelized data to be stored in the 3D clipmap data structure.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 14, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Alexey Panteleev, Yury Uralsky, Evgeny Makarov, Henry Moreton, Sergey Bolotov, Eric Lum, Alexey Barkovoy, Cyril Crassin
  • System, method, and computer program product for tiled screen space sample scrambling for parallel deterministic consistent light transport simulation
    Patent number: 9367955
    Abstract: A system, method, and computer program product are provided for computing values for pixels in an image plane. In use, a low discrepancy sequence associated with an image plane is identified. Additionally, a function with the set of pixels of the image plane as a domain is determined. Further, a value is computed for each pixel in the image plane, utilizing the low discrepancy sequence and the function with the set of pixels of the image plane as a domain.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: June 14, 2016
    Assignee: NVIDIA Corporation
    Inventors: Matthias Raab, Carsten Alexander Wächter, Alexander Keller
  • System and method for propagating scene information to renderers in a multi-user, multi-scene environment
    Patent number: 9367889
    Abstract: A system and method for propagating scene information to a renderer. In one embodiment, the system includes: (1) an update request receiver operable to receive an update request from the renderer and determine a point from which the renderer is to be updated and (2) an update propagator associated with the update request receiver and operable to employ a graph containing scene information to construct a change list corresponding to the update request and transmit the change list toward the renderer.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: June 14, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Julia Flötotto, Stefan Radig
  • Method for forming an integrated circuit package
    Patent number: 9368183
    Abstract: An integrated circuit package includes a packaging substrate with an electrical connection pad formed thereon and an integrated circuit die coupled to the electrical connection pad. The electrical connection pad includes an electroplated surface finish layer, but does not include an electrical trace configured as a plating tail. Because the electrical connection pad is free of a plating tail, signal degradation caused by the presence of plating tails in the integrated circuit package is avoided.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: June 14, 2016
    Assignee: NVIDIA Corporation
    Inventor: Leilei Zhang
  • Method for transforming a multithreaded program for general execution
    Patent number: 9367306
    Abstract: A technique is disclosed for executing a program designed for multi-threaded operation on a general purpose processor. Original source code for the program is transformed from a multi-threaded structure into a computationally equivalent single-threaded structure. A transform operation modifies the original source code to insert code constructs for serial thread execution. The transform operation also replaces synchronization barrier constructs in the original source code with synchronization barrier code that is configured to facilitate serialization. The transformed source code may then be conventionally compiled and advantageously executed on the general purpose processor.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: June 14, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Jaydeep Marathe, Vinod Grover
  • System and method for managing cache replacements
    Patent number: 9367467
    Abstract: A system and method for managing cache replacements and a memory subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a cache controller operable to control a cache and, in order: (1a) issue a pre-fetch command when the cache has a cache miss, (1b) perform at least one housekeeping task to ensure that the cache can store a replacement line and (1c) issue a fetch command and (2) a memory controller associated with a memory of a lower level than the cache and operable to respond to the pre-fetch command by performing at least one housekeeping task to ensure that the memory can provide the replacement line and respond to the fetch command by providing the replacement line.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 14, 2016
    Assignee: Nvidia Corporation
    Inventors: Anurag Chaudhary, Guillermo Rozas
  • Absorbing excess under-fill flow with a solder trench
    Patent number: 9368422
    Abstract: One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: June 14, 2016
    Assignee: NVIDIA Corporation
    Inventors: Leilei Zhang, Ron Boja, Abraham F. Yee, Zuhair Bokharey
  • Graphics processing subsystem and method for recovering a video basic input/output system
    Patent number: 9367399
    Abstract: A graphics processing subsystem and a method for recovering a video basic input/output system (VBIOS). One embodiment of the graphics processing subsystem includes: (1) a memory configured to store a VBIOS, and (2) a processor coupled to the memory and configured to employ a bridge to gain access to the VBIOS and cause the VBIOS to be written to the memory.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 14, 2016
    Assignee: Nvidia Corporation
    Inventors: Rajagopal Sudharsanan, Prasad Raghavendra, Saravanan Sambantham
  • Mitigating main crossbar load using dedicated connections for certain traffic types
    Patent number: 9367487
    Abstract: One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to destination components within the computer system. The control information may belong to various traffic paradigms, such as short-latency data traffic, narrow-width data traffic or broadcast data traffic. The physical connections within the control crossbar unit are categorized based on the different types of control information being transmitted through the control crossbar unit. The physical connections belong to the following categories: one-to-one (OTO) connections, one-to-many (OTM) connections, valid-to-one (VTO) connections, valid-to-many (VTM) connections wire-to-one (WTO) connections and wire-to-many (WTM) connections.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: June 14, 2016
    Assignee: NVIDIA Corporation
    Inventors: Dane Mrazek, Yongxiang Liu, Yin Fung Tang, David Glasco
  • Hardware chip select training for memory using write leveling mechanism
    Patent number: 9368169
    Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: June 14, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam