Patents Assigned to NVidia
  • Patent number: 12056806
    Abstract: Systems and methods of the present disclosure relate to fine grained interleaved rendering applications in path tracing for cloud computing environments. For example, a renderer and a rendering process may be employed for ray or path tracing and image-space filtering that interleaves the pixels of a frame into partial image fields and corresponding reduced-resolution images that are individually processed in parallel. Parallelization techniques described herein may allow for high quality rendered frames in less time, thereby reducing latency (or lag, in gaming applications) in high performance applications.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: August 6, 2024
    Assignee: NVIDIA Corporation
    Inventors: Nuno Raposo Subtil, Manuel Kraemer, Alexey Panteleev, Mike Songy
  • Patent number: 12057113
    Abstract: In various examples, systems and methods of the present disclosure combine open and closed dialog systems into an intelligent dialog management system. A text query may be processed by a natural language understanding model trained to associate the text query with a domain tag, intent classification, and/or input slots. Using the domain tag, the natural language understanding model may identify information in the text query corresponding to input slots needed for answering the text query. The text query and related information may then be passed to a dialog manager to direct the text query to the proper domain dialog system. Responses retrieved from the domain dialog system may be provided to the user via text output and/or via a text to speech component of the dialog management system.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: August 6, 2024
    Assignee: NVIDIA Corporation
    Inventors: Shubhadeep Das, Sumit Bhattacharya, Ratin Kumar
  • Patent number: 12055412
    Abstract: Systems and methods for vehicle-based determination of HD map update information. Sensor-equipped vehicles may determine locations of various detected objects relative to the vehicles. Vehicles may also determine the location of reference objects relative to the vehicles, where the location of the reference objects in an absolute coordinate system is also known. The absolute coordinates of various detected objects may then be determined from the absolute position of the reference objects and the locations of other objects relative to the reference objects. Newly-determined absolute locations of detected objects may then be transmitted to HD map services for updating.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: August 6, 2024
    Assignee: NVIDIA Corporation
    Inventors: Amir Akbarzadeh, Ruchita Bhargava, Bhaven Dedhia, Rambod Jacoby, Jeffrey Liu, Vaibhav Thukral
  • Patent number: 12056494
    Abstract: Apparatuses, systems, and techniques to identify instructions for advanced execution. In at least one embodiment, a processor performs one or more instructions that have been identified by a compiler to be speculatively performed in parallel.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: August 6, 2024
    Assignee: NVIDIA Corporation
    Inventors: Justin Wang, Dz-Ching Ju
  • Patent number: 12057974
    Abstract: A receiver includes a decision feed forward equalization (DFFE) system that generates, based on a digital signal that includes at least one intersymbol interference (ISI) value introduced by a communication channel, a detected signal including a set of detected symbol values. The DFFE system cancels the at least one ISI value from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: August 6, 2024
    Assignee: Nvidia Corporation
    Inventors: Vishnu Balan, Viswanath Annampedu, Pervez Mirzra Aziz
  • Patent number: 12055995
    Abstract: Apparatuses, systems, and techniques to predict a probability of an error or anomaly in processing units, such as those of a data center. In at least one embodiment, the probability of an error occurring in a processing unit is identified using multiple trained machine learning models, in which the trained machine learning models each outputs, for example, the probability of an error occurring within a different predetermined time period.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: August 6, 2024
    Assignee: Nvidia Corporation
    Inventors: Tamar Viclizki, Fay Wang, Divyansh Jain, Avighan Majumder, Vadim Gechman, Vibhor Agrawal
  • Patent number: 12054164
    Abstract: Systems and methods for detecting hardware faults in computer-based feedback control systems. Multiple instances of the system control program(s) are run on system processors. System sensor data are input to each instance, and the control commands output by each instance are compared. As instantiations of the same programs receive largely the same sensor data, differences between output commands may indicate the presence of one or more hardware faults.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: August 6, 2024
    Assignee: NVIDIA Corporation
    Inventors: Tim Tsai, Saurabh Jha, Siva Hari, Michael Sullivan
  • Patent number: 12056854
    Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: August 6, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Thomas Albert Petersen, Ankan Banerjee, Shishir Goyal, Sau Yan Keith Li, Lars Nordskog, Rouslan Dimitrov
  • Publication number: 20240256831
    Abstract: In various examples, systems and methods are disclosed relating to generating a response from image and/or video input for image/video-based artificial intelligence (AI) systems and applications. Systems and methods are disclosed for a first model (e.g., a teacher model) distilling its knowledge to a second model (a student model). The second model receives a downstream image in a downstream task and generates at least one feature. The first model generates first features corresponding to an image which can be a real image or a synthetic image. The second model generates second features using the image as an input to the second model. Loss with respect to first features is determined. The second model is updated using the loss.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Applicant: NVIDIA Corporation
    Inventors: Daiqing Li, Huan Ling, Seung Wook Kim, Karsten Julian Kreis, Antonio Torralba Barriuso, Sanja Fidler, Amlan Kar
  • Patent number: 12051332
    Abstract: In various examples, a path perception ensemble is used to produce a more accurate and reliable understanding of a driving surface and/or a path there through. For example, an analysis of a plurality of path perception inputs provides testability and reliability for accurate and redundant lane mapping and/or path planning in real-time or near real-time. By incorporating a plurality of separate path perception computations, a means of metricizing path perception correctness, quality, and reliability is provided by analyzing whether and how much the individual path perception signals agree or disagree. By implementing this approach—where individual path perception inputs fail in almost independent ways—a system failure is less statistically likely. In addition, with diversity and redundancy in path perception, comfortable lane keeping on high curvature roads, under severe road conditions, and/or at complex intersections.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: July 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Davide Marco Onofrio, Hae-Jong Seo, David Nister, Minwoo Park, Neda Cvijetic
  • Patent number: 12050548
    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: July 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P Singh, Ching-Yu Hung
  • Patent number: 12050893
    Abstract: Systems and methods related to generating machine code using a coroutine suspension mechanism are disclosed below. An asynchronous programming model utilizing coroutines may be implemented in a compiler for a high-level programming language. The compiler is configured to include functionality related to an intrinsic function for a suspend operation of a coroutine. In accordance with an aspect of the disclosure, a method is disclosed for generating machine code that includes the coroutine mechanism. The method includes: receiving source code for a program in a high-level programming language, and compiling the source code with a compiler to generate machine code for a target processor. The source code includes a caller and a coroutine called by the caller. The compiler is configured to detect an intrinsic function for a suspend operation in the source code for the coroutine. The compiler inserts low-level code in the machine code in accordance with an ABI.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: July 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Konstantinos Kyriakopoulos, Michael F. Haidl, Ralf Andreas Karrenberg, Zhiwei Cao, Gokul Ramaswamy Hirisave Chandra Shekhara, Girish Bhaskarrao Bharambe, Justin Andrew Holewinski, Bharath Vasudevan
  • Patent number: 12047595
    Abstract: Systems and methods herein address reference frame selection in video streaming applications using one or more processing units to decode a frame of an encoded video stream that uses an inter-frame depicting an object and an intra-frame depicting the object, the intra-frame being included in a set of intra-frames based at least in part on at least one attribute of the object as depicted in the intra-frame being different from the at least one attribute of the object as depicted in other intra-frames of the set of intra-frames.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: July 23, 2024
    Assignee: Nvidia Corporation
    Inventors: Aurobinda Maharana, Arun Mallya, Ming-Yu Liu, Abhijit Patait
  • Patent number: 12045666
    Abstract: Apparatuses, systems, and techniques to collect performance data for one or more computations tasks executed by a plurality of nodes of a computational pipeline and enable optimization of distribution of task execution among the plurality of nodes.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: July 23, 2024
    Assignee: Nvidia Corporation
    Inventors: Shekhar Dwivedi, Rahul Choudhury
  • Patent number: 12045952
    Abstract: Apparatuses, systems, and techniques to enhance video are disclosed. In at least one embodiment, one or more neural networks are used to create a higher resolution video using upsampled frames from a lower resolution video.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: July 23, 2024
    Assignee: NVIDIA Corporation
    Inventors: Shiqiu Liu, Matthieu Le, Andrew Tao
  • Patent number: 12044732
    Abstract: Silicon test structures are described that enable separate measurement of n-channel metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor (PMOS) transistor delays. NMOS and PMOS specific non-inverting stages may be used to construct a multi-stage ring oscillator. Each of the non-inverting stages generates either a rising or falling primary transition that is determined by either NMOS or PMOS transistors, respectively. The opposing transition for a particular non-inverting stage is triggered by propagation of the primary transition to a subsequent non-inverting stage (producing a “reset” pulse). A frequency of the ring oscillator is determined by the primary transition and one transistor type (NMOS or PMOS). Specifically, the frequency is determined by the propagation delay of the primary transition through the entire ring oscillator.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: July 23, 2024
    Assignee: NVIDIA Corporation
    Inventors: Prashant Singh, Tezaswi Vatsavai Raja
  • Patent number: 12045924
    Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: July 23, 2024
    Assignee: NVIDIA Corporation
    Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
  • Patent number: 12046006
    Abstract: According to an aspect of an embodiment, operations may comprise receiving a LIDAR scan of a scene from a LIDAR of a vehicle with the scene comprising a board, detecting the board in the LIDAR scan, fitting a plane through LIDAR coordinates corresponding to the detected board, projecting the plane from the LIDAR coordinates to a first set of camera coordinates, detecting the board in a camera image from a camera of the vehicle at a second set of camera coordinates, and calibrating the LIDAR of the vehicle and the camera of the vehicle by determining a transform between the first set of camera coordinates and the second set of camera coordinates.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: July 23, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Zhengyu Zhang, Lin Yang, Mark Damon Wheeler
  • Patent number: 12045307
    Abstract: Today neural networks are used to enable autonomous vehicles and improve the quality of speech recognition, real-time language translation, and online search optimizations. However, operation of the neural networks for these applications consumes energy. Quantization of parameters used by the neural networks reduces the amount of memory needed to store the parameters while also reducing the power consumed during operation of the neural network. Matrix operations performed by the neural networks require many multiplication calculations, so reducing the number of bits that are multiplied reduces the energy that is consumed. Quantizing smaller sets of the parameters using a shared scale factor improves accuracy compared with quantizing larger sets of the parameters. Accuracy of the calculations may be maintained by quantizing and scaling the parameters using fine-grained per-vector scale factors. A vector includes one or more elements within a single dimension of a multi-dimensional matrix.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 23, 2024
    Assignee: NVIDIA Corporation
    Inventors: Brucek Kurdo Khailany, Steve Haihang Dai, Rangharajan Venkatesan, Haoxing Ren
  • Patent number: 12047067
    Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: July 23, 2024
    Assignee: NVIDIA CORP.
    Inventors: Walker Joseph Turner, John Poulton, Sanquan Song