Patents Assigned to NVidia
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Patent number: 12111177Abstract: According to an aspect of an embodiment, operations may comprise receiving sensor data from one or more vehicles, determining, by combining the received sensor data, a high definition map comprising a point cloud, and labeling one or more objects in the point cloud. The operations may also comprise generating training data by receiving a new image captured by one of the vehicles, receiving a pose of the vehicle when the new image was captured, determining an object having a label in the point cloud that is observable from the pose of the vehicle, determining a position of the object in the new image, and labeling the new image by assigning the label of the object to the new image, the labeled new image comprising the training data. The operations may also comprise training a deep learning model using the training data.Type: GrantFiled: July 2, 2020Date of Patent: October 8, 2024Assignee: NVIDIA CORPORATIONInventors: Yu Zhang, Lin Yang
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Patent number: 12109701Abstract: A robot is controlled using a combination of model-based and model-free control methods. In some examples, the model-based method uses a physical model of the environment around the robot to guide the robot. The physical model is oriented using a perception system such as a camera. Characteristics of the perception system may be are used to determine an uncertainty for the model. Based at least in part on this uncertainty, the system transitions from the model-based method to a model-free method where, in some embodiments, information provided directly from the perception system is used to direct the robot without reliance on the physical model.Type: GrantFiled: February 3, 2020Date of Patent: October 8, 2024Assignee: NVIDIA CorporationInventors: Jonathan Tremblay, Dieter Fox, Michelle Lee, Carlos Florensa, Nathan Donald Ratliff, Animesh Garg, Fabio Tozeto Ramos
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Patent number: 12112147Abstract: Systems and methods are disclosed that relate to graphically representing different components (e.g., software modules, libraries, interfaces, or other blocks of code) that may be included in an application, linking the components in an ordered sequence to embody the application, and deploying the application to perform a task. The components may be displayed and represented as graphical components in a graphical application editor, or any other development environment. The graphical application editor may perform various operations with respect to the graphical components and the components respectively represented by and corresponding therewith. The operations may include facilitation of linking implemented instances of the graphical component objects together and/or developing the application by linking the underlying code associated with the graphical component objects according to the linking of the graphical component objects.Type: GrantFiled: June 8, 2022Date of Patent: October 8, 2024Assignee: NVIDIA CORPORATIONInventors: Chunlin Li, Prashant Gaikwad, Kaustabh Purandare
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Patent number: 12112247Abstract: In various examples, object detections of a machine learning model are leveraged to automatically generate new ground truth data for images captured at different perspectives. The machine learning model may generate a prediction of a detected object at the different perspective, and an object tracking algorithm may be used to track the object through other images in a sequence of images where the machine learning model may not have detected the object. New ground truth data may be generated as a result of the object tracking algorithms outputs, and the new ground truth data may be used to retrain or update the machine learning model, train a different machine learning model, or increase the robustness of a ground truth data set that may be used for training machine learning models from various perspectives.Type: GrantFiled: September 28, 2023Date of Patent: October 8, 2024Assignee: NVIDIA CorporationInventor: Eric Todd Brower
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Patent number: 12112395Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.Type: GrantFiled: July 2, 2020Date of Patent: October 8, 2024Assignee: NVIDIA CorporationInventors: Stephen Jones, Vivek Kini, Piotr Jaroszynski, Mark Hairgrove, David Fontaine, Cameron Buschardt, Lucien Dunning, John Hubbard
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Publication number: 20240332223Abstract: An integrated circuit die substrate has one or more capacitors attached to an edge surface of the substrate. The substrate has a top surface and a bottom surface, at least one of which includes a die mounting area, and at least one of which includes system interconnect terminals. A substrate edge surface is disposed along a peripheral end of the substrate and is oriented substantially orthogonally to the top and bottom surfaces. A pair of conductive edge terminals is disposed on the substrate edge surface. Each of the edge terminals is electrically coupled to a respective substrate conductor disposed on or inside the substrate. A capacitor is attached exteriorly to the substrate at the substrate edge surface such that terminals of the capacitor are electrically coupled to respective ones of the edge terminals. An integrated circuit die is attached at the die mounting area.Type: ApplicationFiled: March 5, 2024Publication date: October 3, 2024Applicant: NVIDIA CorporationInventors: Tracy Fu, Tiger Yan, Joey Cai, Zach Wang
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Patent number: 12105960Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.Type: GrantFiled: August 31, 2022Date of Patent: October 1, 2024Assignee: NVIDIA CORPORATIONInventors: Srinivas Santosh Kumar Madugula, Olivier Giroux, Wishwesh Anil Gandhi, Michael Allen Parker, Raghuram L, Ivan Tanasic, Manan Patel, Mark Hummel, Alexander L. Minkin
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Patent number: 12106423Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.Type: GrantFiled: September 16, 2022Date of Patent: October 1, 2024Assignee: NVIDIA CORPORATIONInventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
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Publication number: 20240319713Abstract: In various examples, systems and methods are disclosed relating to decider networks for reactive decision-making, including for control of robotic systems. The decider networks can allow robotic systems to operate more collaboratively, such as by allowing the robotic systems to more frequently process and react to dynamic states of the environment and objects in the environment, such as to change decisions and/or paths of decision execution responsive to dynamic changes in logical states. The decider network can include a plurality of nodes having functions to process the logical states in sequence to determine actions for the robotic systems to perform.Type: ApplicationFiled: May 23, 2023Publication date: September 26, 2024Applicant: NVIDIA CorporationInventor: Nathan Donald Ratliff
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Publication number: 20240322559Abstract: An integrated circuit that includes multiple power rails with dummy loads configured on at least some of the power rails. The dummy loads are activated in response to a voltage overshoot condition on regions of the power rails at which the dummy loads are located. The dummy loads may be substituted for decoupling capacitors or other active cells at particular regions of the power rails.Type: ApplicationFiled: March 20, 2023Publication date: September 26, 2024Applicant: NVIDIA Corp.Inventors: Tezaswi Raja, Abhishek B Akkur, Jun Gu, Chengcheng Liu
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Patent number: 12100112Abstract: A content management system may maintain a scene description that represents a 3D virtual environment and a publish/subscribe model in which clients subscribe to content items that correspond to respective portions of the shared scene description. When changes are made to content, the changes may be served to subscribing clients. Rather than transferring entire descriptions of assets to propagate changes, differences between versions of content may be exchanged, which may be used construct updated versions of the content. Portions of scene description may reference other content items and clients may determine whether to request and load these content items for lazy loading. Content items may be identified by Uniform Resource Identifiers (URIs) used to reference the content items. The content management system may maintain states for client connections including for authentication, for the set of subscriptions in the publish/subscribe model, and for their corresponding version identifiers.Type: GrantFiled: December 3, 2021Date of Patent: September 24, 2024Assignee: NVIDIA CorporationInventors: Rev Lebaredian, Michael Kass, Brian Harris, Andrey Shulzhenko, Dmitry Duka
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Patent number: 12099848Abstract: Apparatuses, systems, and techniques to receive, by a processor of a computer system, one or more operations for a kernel; automatically generate, by the processor, one or more operators that perform the one or more operations on elements of one or more input data structures; and automatically generate, by the processor, the kernel that comprises the one or more operators.Type: GrantFiled: July 29, 2021Date of Patent: September 24, 2024Assignee: Nvidia CorporationInventors: Justin Paul Luitjens, Clifford Keith Burdick, Jacob Ryan Hemstad
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Patent number: 12101907Abstract: Systems and methods for cooling a mobile datacenter are disclosed. In at least one embodiment, a cooling loop is located on a mobile unit and includes at least one cold plate within a pod on a mobile unit and includes a dry cooler external to a pod on a mobile unit so as to enable coolant to be provided to a cold plate and to enable such coolant to be provided to a dry cooler for removal of heat from at least one computing device to an ambient environment.Type: GrantFiled: April 30, 2021Date of Patent: September 24, 2024Assignee: Nvidia CorporationInventor: Ali Heydari
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Patent number: 12099453Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.Type: GrantFiled: March 30, 2022Date of Patent: September 24, 2024Assignee: NVIDIA CorporationInventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
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Patent number: 12099439Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.Type: GrantFiled: August 2, 2021Date of Patent: September 24, 2024Assignee: NVIDIA CorporationInventors: Ching-Yu Hung, Ravi P Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani
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Patent number: 12101338Abstract: Various approaches are disclosed for protecting vehicle buses from cyber-attacks. Disclosed approaches provide for an embedded system having a hypervisor that provides a virtualized environment supporting any number of guest OSes. The virtualized environment may include a security engine on an internal communication channel between the guest OS and an external vehicle bus of a vehicle to analyze network traffic to protect the guest OS from other guest OSes or other network components, and to protect those network components from the guest OS. Each guest OS may have its own security engine customized for the guest OS to account for what is typical or expected traffic for the guest OS (e.g., using machine learning, anomaly detection, etc.). Also disclosed are approaches for corrupting a message being transmitted on a vehicle bus to prevent devices from acting on the message.Type: GrantFiled: June 7, 2019Date of Patent: September 24, 2024Assignee: NVIDIA CorporationInventors: Mark Overby, Rick Dingle, Nicola Di Miscio, Varadharajan Kannan, Yong Zhang, Francesco Saracino
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Patent number: 12100113Abstract: In order to determine accurate three-dimensional (3D) models for objects within a video, the objects are first identified and tracked within the video, and a pose and shape are estimated for these tracked objects. A translation and global orientation are removed from the tracked objects to determine local motion for the objects, and motion infilling is performed to fill in any missing portions for the object within the video. A global trajectory is then determined for the objects within the video, and the infilled motion and global trajectory are then used to determine infilled global motion for the object within the video. This enables the accurate depiction of each object as a 3D pose sequence for that model that accounts for occlusions and global factors within the video.Type: GrantFiled: January 25, 2022Date of Patent: September 24, 2024Assignee: NVIDIA CORPORATIONInventors: Ye Yuan, Umar Iqbal, Pavlo Molchanov, Jan Kautz
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Patent number: 12099407Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.Type: GrantFiled: May 5, 2022Date of Patent: September 24, 2024Assignee: NVIDIA CORP.Inventors: Michael Sullivan, Siva Kumar Sastry Hari, Brian Matthew Zimmer, Timothy Tsai, Stephen W. Keckler
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Publication number: 20240312123Abstract: In various examples, systems and methods are disclosed that relate to data augmentation for training/updating perception models in autonomous or semi-autonomous systems and applications. For example, a system may receive data associated with a set of frames that are captured using a plurality of cameras positioned in fixed relation relative to the machine; generate a panoramic view based at least on the set of frames; provide data associated with the panoramic view to a model to cause the model to generate a high dynamic range (HDR) panoramic view; determine lighting information associated with a light distribution map based at least on the HDR panoramic view; determine a virtual scene; and render an asset and a shadow on at least one of the frames, based at least on the virtual scene and the light distribution map, the shadow being a shadow corresponding to the asset.Type: ApplicationFiled: February 29, 2024Publication date: September 19, 2024Applicant: NVIDIA CorporationInventors: Malik Aqeel Anwar, Tae Eun Choe, Zian Wang, Sanja Fidler, Minwoo Park
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Patent number: 12092820Abstract: Virtual reality (VR) displays are computer displays that present images or video in a manner that simulates a real experience for the viewer. In many cases, VR displays are implemented as head-mounted displays (HMDs) which provide a display in the line of sight of the user. Because current HMDs are composed of a display panel and magnifying lens with a gap therebetween, proper functioning of the HMDs limits their design to a box-like form factor, thereby negatively impacting both comfort and aesthetics. The present disclosure provides a different configuration for a virtual reality display which allows for improved comfort and aesthetics, including specifically at least one coherent light source, at least one holographic waveguide coupled to the at least one coherent light source to receive light therefrom, and at least one spatial light modulator coupled to the at least one holographic waveguide to modulate the light.Type: GrantFiled: September 14, 2021Date of Patent: September 17, 2024Assignee: NVIDIA CORPORATIONInventors: Jonghyun Kim, Ward Lopes, David Luebke, Manu Gopakumar