Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

Abstract: Methods, systems, and devices are provided herein for a mechanism to identify link down reasons. As described herein, a first port of a first peer device may be determined to have unexpectedly changed to a port down state. Subsequently, a topology file may be referenced to identify a second port of a second peer device with which the first peer device is intended to have a link if not for the first port being in a port down state. In some examples, port settings of the first port may be compared with port settings of the second port. If a port setting for the first port mismatches an associated port setting for the second port, an alert message may be transmitted to a network administrator indicating this mismatch as a possible reason for the first port being in the port down state.

Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

Abstract: Embodiments of the present invention provide a novel solution that uses subjective end-user input to generate optimal image quality settings for an application. Embodiments of the present invention enable end-users to rank and/or select various adjustable application parameter settings in a manner that allows them to specify which application parameters and/or settings are most desirable to them for a given application. Based on the feedback received from end-users, embodiments of the present invention may generate optimal settings for whatever performance level the end-user desires. Furthermore, embodiments of the present invention may generate optimal settings that may be benchmarked either on a server farm or on an end-user's client device.

Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

Abstract: Apparatuses, systems, and techniques to estimate or predict depth information for image data. In at least one embodiment, depth information is predicted based at least in part on color information and geometry information associated with an image.

Abstract: Self-supervised machine learning is applied to combinational gate sizing based on an input circuit netlist. A transformer neural network architecture is disclosed to select gate sizes along paths of the network between primary inputs/outputs and/or sequential logic elements. The gate size selections may be optimized along dimensions such as path delay, path power consumption, and path circuit area.

Abstract: In various examples, systems and methods are disclosed relating to aliasing control of program variables in storage via automatic application of artificial dependences during program compilation. In some implementations, a system can include a detector to automatically detect a pattern, based at least on a structure of data flow in a source program, indicative of sequences of dependent operations, where the sequences are independent from one another. The system can determine a storage aliasing preference for whether to allow the compiler to allocate the program variables of the respective sequences to the same processor storage locations, or to prevent the compiler from doing so. The system can assign one or more annotations to the source program indicative of one or more artificial dependences for a compiler to respect when performing program transformations prior to the allocation of program variables.

Abstract: A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.

Abstract: The disclosure provides a learning framework that unifies both semantic segmentation and semantic edge detection. A learnable recurrent message passing layer is disclosed where semantic edges are considered as explicitly learned gating signals to refine segmentation and improve dense prediction quality by finding compact structures for message paths. The disclosure includes a method for coupled segmentation and edge learning. In one example, the method includes: (1) receiving an input image, (2) generating, from the input image, a semantic feature map, an affinity map, and a semantic edge map from a single backbone network of a convolutional neural network (CNN), and (3) producing a refined semantic feature map by smoothing pixels of the semantic feature map using spatial propagation, and controlling the smoothing using both affinity values from the affinity map and edge values from the semantic edge map.

Abstract: Various techniques for adaptive rendering of images with noise reduction are described. More specifically, the present disclosure relates to approaches for rendering and denoising images—such as ray-traced images—in an iterative process that distributes computational efforts to pixels where denoised output is predicted with higher uncertainty. In some embodiments, an input image may be fed into a deep neural network (DNN) to jointly predict a denoised image and an uncertainty map. The uncertainty map may be used to create a distribution of additional samples (e.g., for one or more samples per pixel on average), and the additional samples may be used with the input image to adaptively render a higher quality image. This process may be repeated in a loop, until some criterion is satisfied, for example, when the denoised image converges to a designated quality, a time or sampling budget is satisfied, or otherwise.

Abstract: Optical center is determined on a column-by-column and row-by-row basis by identifying brightest pixels in respective columns and rows. The brightest pixels in each column are identified and a line is fit to those pixels. Similarly, brightest pixels in each row are identified and a second line is fit to those pixels. The intersection of the two lines is the optical center.

Abstract: In various examples, systems and methods are disclosed herein for a vehicle command operation system that may use technology across multiple modalities to cause vehicular operations to be performed in response to determining a focal point based on a gaze of an occupant. The system may utilize sensors to receive first data indicative of an eye gaze of an occupant of the vehicle. The system may utilize sensors to receive second data indicative of other data from the occupant. The system may then calculate a gaze vector based on the data indicative of the eye gaze of the occupant. The system may determine a focal point based on the gaze vector. In response to determining the focal point, the system causes an operation to be performed in the vehicle based on the second data.

Abstract: A combined on-package and off-package memory system uses a custom base-layer within which are fabricated one or more dedicated interfaces to off-package memories. An on-package processor and on-package memories are also directly coupled to the custom base-layer. The custom base-layer includes memory management logic between the processor and memories (both off and on package) to steer requests. The memories are exposed as a combined memory space having greater bandwidth and capacity compared with either the off-package memories or the on-package memories alone. The memory management logic services requests while maintaining quality of service (QoS) to satisfy bandwidth requirements for each allocation. An allocation may include any combination of the on and/or off package memories. The memory management logic also manages data migration between the on and off package memories.

Abstract: Apparatuses, systems, and techniques to determine precoding weights for fifth-generation (5G) new radio (NR) downlink transmission in parallel. In at least one embodiment, a parallel processor includes one or more circuits to perform precoding for a 5G downlink signal using two or more processing threads in parallel.

Abstract: Embodiments of the present invention provide a low-latency approach for local or remote application streaming that reaches high FPS targets without overloading the available streaming bandwidth, for example, by limiting the bit rate to the same value that is used by traditional 60 FPS streaming solutions. A client device and server device cooperate to actively monitor and control a video stream to maintain an acceptable balance between latency and video quality by adjusting the frequency or resolution when necessary to improve the streaming experience. When the server device captures and transmits frames at a higher rate, the software stack executing on the client device is able to display frames with less delay, even on a display device limited to 60 Hz, thereby achieving additional latency reduction.

Abstract: Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.