Abstract: A first error-correcting decoder, adapted to decode the data bits of a received OFDM symbol; a re-encoder, to receive decoded bits and adapted to re-encode a leading portion of the decoded bits; a mapper, to receive the re-encoded leading portion of bits, map these bits to a corresponding subset of the plurality of sub-carriers, and thereby estimate a modulation symbol that was applied to each sub-carrier of said subset a channel estimator, to produce a channel estimate by comparing the sub-carrier modulation symbols with the corresponding sub-carriers actually received by the receiver; and an equalizer, to process the received signal to remove distortions introduced by the transmission channel, using the channel estimate, the re-encoder is adapted to begin re-encoding the leading portion of the bits before a trailing portion of the bits has been decoded by the decoder.

Abstract: Embodiments of a method for controlling a charge pump and a control device for a charge pump are described. In one embodiment, a method for controlling a charge pump involves monitoring a power-on status of the charge pump, calculating a duty cycle of the charge pump within a time period based on the power-on status of the charge pump, and adjusting at least one of a clock frequency setting and a capacitance setting of the charge pump in based on the duty cycle of the charge pump. Other embodiments are also described.

Abstract: An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptic Curve Cryptography point addition algorithm for mixed Affine-Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values.

Abstract: RF repeater circuits may be used to regenerate an RF signal. A method and apparatus is described for regenerating a received RF signal the RF signal comprising a plurality of channels, each channel comprising a plurality of channel symbols, the method comprising producing a digitized RF signal from the received RF signal, extracting spectral information of each of the channels from the digitized RF signal, recovering one or more channel symbols from each of the plurality of channels, remodulating the channel symbols, and converting the remodulated channel symbols to an analog signal resulting in a regenerated RF signal.

Abstract: A mobile device, including: a wireless communication interface; a memory storing a secure software application; and a processor in communication with the memory, the processor being configured to: transmit an authentication challenge to the SIM card; receive an authentication response from the SIM card; verify the authentication response from the SIM card; and enable the secure software application when the authentication response from the SIM card is verified.

Abstract: Switching circuits are implemented in a manner that facilitates fast switching, which can be effected while also maintaining relatively low power dissipation. As may be implemented in connection with one or more embodiments, an apparatus includes a transistor connected between an input port and an output port, and a gate that switches between on and off states. A charge storage circuit stores a charge, and a switching circuit operates by switching the transistor between the on and off states as follows. In a first charging mode, a voltage is coupled across the charge storage circuit and a charge is stored therein, while decoupling the transistor from the charge storage circuit. In a second discharge mode, the transistor is switched from the off state to the on state, while coupling the stored charge across the gate and one of the source and drain of the transistor.

Abstract: An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptical Curve Cryptography point doubling algorithm for Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values to one intermediate value.

Abstract: Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate. A body bias circuit is configured to bias the body of the transistor based on a voltage of the data signal to reduce variation in the on-resistance exhibited by the first transistor. In an embodiment, the apparatus includes body bias transistors and switches and the gates of the body bias transistors are connected to protect the body bias transistors from the effects of electrostatic discharge (ESD) events.

Abstract: Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate. A body bias circuit is configured to bias the body of the transistor based on a voltage of the data signal to reduce variation in the on-resistance exhibited by the first transistor. As a result of the reduced variation in the on resistance, attenuation of the data signal is reduced.

Abstract: An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptical Curve Cryptography point doubling algorithm for Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values.

Abstract: An RF receiver is disclosed. The RF receiver includes an analog-to-digital converter for converting an analog intermediate frequency band signal to a digital intermediate frequency band signal. A plurality of decimation units coupled in cascade for generating a decimated signal based on the digital intermediate frequency band signal are also included. The RF receiver further includes a signal processing unit for processing the decimated signal and a bypass path for feeding a bypass signal to the signal processing unit. The bypass signal is either the digital intermediate frequency band signal or an output signal from one of the decimation units which is not the last one of the cascade coupled decimation units. The signal processing unit is adapted to detect critical reception conditions based on the bypass signal and to adapt the processing of the decimated signal in accordance with detected critical reception conditions.

Abstract: Consistent with an example embodiment there is a method of controlling a resonant power converter; the power converter includes first and second series connected switches connected between a supply voltage line and a ground line and a resonance circuit, having a capacitor and an inductor. The resonance circuit is connected to a node connecting the first and second switches. The method comprises repeated sequential steps of closing the first switch to start a conduction interval; sampling a voltage across the capacitor to obtain a sampled voltage level; and opening the first switch to end the conduction interval when a voltage across the capacitor crosses a voltage level determined by addition of the sampled voltage level with a predetermined voltage difference; wherein controlling the predetermined voltage difference determines a power output of the resonant power converter.

Abstract: A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.

Abstract: A MEMS microphone has a support surface, a microphone substrate over the support surface and an assembly of a microphone membrane and spaced back electrode supported over the substrate. The substrate has an opening beneath the assembly. The interface between the support surface and the substrate comprises a plurality of discrete spaced portions. This structure provides some resilience to differential expansion and contraction that can arise during processing. The support surface can then be a different material to the substrate, for example a PCB laminate as the support surface and silicon as the substrate.

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: A controller for a switched mode power supply, the switched mode power supply comprising one or more windings. The controller comprising a fixed speed timer; a threshold setter configured to set a threshold for the timer in accordance with a peak value of a current through one of the one or more windings; a secondary stroke detector configured to start the fixed speed timer upon detection of the start of a secondary stroke of the switched mode power supply; a sampler configured to sample a voltage across one of the one or more windings when a count of the fixed speed timer reaches the threshold.

Abstract: A sensor circuit is configured for operation under conditions susceptible to misalignment or movement. In connection with various example embodiments, an alignment-tolerant sensor arrangement includes a reference component and first and second magnetic sensors. The reference component influences a magnetic field as a function of a position of the reference component, such as via the positioning of a magnetic type of component. The first magnetic sensor is aligned with a first magnetic field sensitivity direction, and exhibits an electrical response to the presence of the magnetic field. The second magnetic sensor is aligned with a first magnetic field sensitivity direction and is configured to exhibit an electrical response to the presence of the magnetic field. The first and second magnetic field sensitivity directions being offset from one another to facilitate detection of magnetic fields at different relative alignments between the reference component and the first and second magnetic sensors.

Abstract: There is described a method for initializing a secure element (112, 122, 212, 222) for use with a host unit (121, 221), the method comprising (a) storing a set of initial keys and a master key in a memory of a secure element (112, 122, 212, 222), (b) providing an identifier of a host (121, 221) unit associated with the secure element, (c) generating a modified set of keys based on the initial set of keys, the master key and the identifier of the host unit, and (d) storing the modified set of keys in the memory of the secure element. There is also described a secure element (112, 122, 212, 222) adapted for being embedded into a host unit (121, 221). Furthermore, there is described a system for initializing a secure element, a computer program and a computer program product.

Abstract: A circuit for a switched mode power supply having a winding. The circuit comprising: an input configured to receive a winding voltage derived from the winding; a differentiation element configured to differentiate the winding voltage with respect to time in order to determine a derivative signal and compare the derivative signal with a threshold value; a steady state detector configured to set a zero derivative signal when the derivative signal has not exceeded the threshold value for a predetermined period of time, and a logic arrangement configured to identify an end of a demagnetization stroke of the switched mode power supply when the derivative signal crosses a final threshold value after the zero derivative signal has been set.

Abstract: A controller for an SMPS is disclosed. The controller applies a frequency jitter to the SMPS to reduce Electromagnetic Interference (EMI) and/or audible noise. A second input variable is multiplied by a correlated jitter signal, in order to compensate the output power for the frequency jitter. A corresponding method is also disclosed. Since the jitter compensation occurs within the controller, the method is particularly suitable for controllers operating under different control modes for different output powers (or other output criteria). The multiplicative compensation is applicable across a wide range of converter types.