Abstract: A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes.
Type:
Grant
Filed:
November 21, 2012
Date of Patent:
June 2, 2015
Assignee:
NXP B.V.
Inventors:
Phil Rutter, Ian Culshaw, Steven Thomas Peake
Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.
Abstract: An analog to digital converter comprises an input terminal configured to receive an analog input signal and an output terminal configured to provide an output digital signal.
Abstract: Various embodiments relate to a method, machine-readable medium, and a system for preventing demagnetization of a magnetically sensitive object comprising detecting, by a first identification sensor at a wireless charging transceiver, a foreign object; determining, by a processor using information from the first identification sensor, whether the foreign object is magnetically sensitive; and responsive to a determination that the foreign object is magnetically sensitive, preventing the wireless charging transceiver from operating.
Abstract: The present invention provides for an electronic device having cryptographic computation means arranged to generate cryptographic data within the device for enhancing security of communications therewith, the device including an onboard power supplying means arranged to provide for the driving of the said cryptographic computational means, and so as to provide a device by way of a manufacturing phase and a post manufacturing phase arranged for distribution and/or marketing of the device, and wherein the step of generating the cryptographic data occurs during the post manufacturing phase.
Abstract: Differential amplifier circuits for LDMOS-based amplifiers are disclosed. The differential amplifier circuits comprise a high resistivity substrate and separate DC and AC ground connections. Such amplifier circuits may not require thru-substrate vias for ground connection.
Abstract: A method of operating a switched-mode power supply (SMPS) for supplying power to a load circuit, which draws a supply current that varies with an input signal to the load circuit is disclosed. The method comprises monitoring the input signal and controlling the amount of accumulated energy transferred for consumption by the load circuit, in use, in accordance with the input signal.
Type:
Grant
Filed:
March 20, 2013
Date of Patent:
May 26, 2015
Assignee:
NXP B.V.
Inventors:
Benno Krabbenborg, Marco Berkhout, Johan Somberg, Peter Van De Haar
Abstract: A loudspeaker drive circuit has a microphone which forms part of an acoustic echo cancellation system. An input signal is processed before application to a loudspeaker driver, and the processing is controlled in dependence on the echo cancellation system performance, such as to control the extent to which the loudspeaker is driven into a non-linear operating region. In this way, the linearity can be controlled so as to provide an excursion limit, without needing a model of the loudspeaker or additional dedicated sensors.
Abstract: An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown.
Type:
Grant
Filed:
August 9, 2006
Date of Patent:
May 26, 2015
Assignee:
NXP B.V.
Inventors:
Erik J. Marinissen, Sandeep Kumar Goel, Andre K. Nieuwland, Hubertus G. H. Vermuelen, Hendrikus P. E. Vranken
Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.
Type:
Grant
Filed:
August 5, 2009
Date of Patent:
May 26, 2015
Assignee:
NXP, B.V.
Inventors:
Guillaume Boccardi, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Li Jen Choi, Stefaan Decoutere, Arturo Sibaja-Hernandez, Stefaan Van Huylenbroeck, Rafael Venegas
Abstract: The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part.
Type:
Grant
Filed:
October 4, 2011
Date of Patent:
May 26, 2015
Assignee:
NXP, B.V.
Inventors:
Ghiath Al-Kadi, Massimo Ciacci, Remco Cornelis Herman van de Beek
Abstract: A method for completing a transaction at a terminal between a terminal and a mobile device including: initiating a transaction at the terminal; initiating communication with the mobile device; determining that the mobile device is without power; transmitting a wireless power signal to power the mobile device; sending a transaction authentication request message to the mobile device after transmitting the wireless power signal; receiving an authentication message from the mobile device; and completing the transaction after receiving the authentication message from the mobile device.
Type:
Application
Filed:
November 15, 2013
Publication date:
May 21, 2015
Applicant:
NXP B.V.
Inventors:
Kai Neumann, Johannes van Lammeren, Klaas Brink
Abstract: A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.
Type:
Application
Filed:
November 18, 2013
Publication date:
May 21, 2015
Applicant:
NXP B.V.
Inventors:
Juan Diego Echeverri Escobar, Jose de Jesus Pineda de Gyvez
Abstract: According to an aspect of the invention, a security token is conceived, in particular a smart card, comprising a tactile sensing user interface, wherein said tactile sensing user interface is adapted to capture a stream of authentication data corresponding to a sequence of positions of a finger engaging with said tactile sensing user interface and representing a user-specific credential for accessing at least one function of a controllable object, said security token being adapted to transmit said stream of authentication data to the controllable object in order to access said function.
Abstract: An apparatus, method and package for electronic tamper detection. In one example, an apparatus, device or package for electronic tamper detection includes: a first inductor positioned at a first distance from a first conductive surface; a first oscillator generating a first frequency in dependence upon the first inductor; and a comparator setting a tamper detected status if the generated first frequency is not within an error tolerance to a pre-stored first frequency. One example of a method for fabricating an electronic tamper detection apparatus, device, or package is also provided.
Abstract: An electronic device incorporating a randomized interconnection layer. In one example, the device includes a randomized interconnection layer having a randomized conductive pattern formed by etching of a heterogeneous layer; and a sensing circuit, electrically coupled to the randomized interconnection layer to detect the randomized conductive pattern. In another example, a method of fabricating the device includes forming a set of electrodes proximate to a silicon substrate; depositing a heterogeneous layer of elements onto the substrate; etching the heterogeneous layer to form a randomized conductive pattern; and electrically coupling the electrodes to a sensing circuit and the randomized conductive pattern.
Type:
Application
Filed:
November 21, 2013
Publication date:
May 21, 2015
Applicant:
NXP B.V.
Inventors:
Michael Antoine Armand in 't Zandt, Viet Hoang Nguyen
Abstract: Various aspects are directed to providing an output/state based upon an input value. Consistent with one or more embodiments, an apparatus includes a bias circuit that is connected between power and common rails and includes first and second current paths that provide first and second reference currents. A current-mirroring circuit provides a first mirrored current in response to a voltage input transitioning in a first direction between voltage levels, and a second mirrored current in response to a voltage input transitioning in an opposite direction. A logic circuit operates in a first state based upon the first mirrored current and the first reference current, and operates in a second state based upon the second mirrored current and the second reference current.
Abstract: Temperature characteristics of battery cells are detected. In accordance with one or more embodiments, an intercept frequency is detected for each battery cell, at which frequency an imaginary part of a plot of impedance values of the battery cell exhibits a zero crossing. The impedance values correspond to current injected into the cell. A temperature of the cell is determined based upon the detected intercept frequency for the cell and stored data that models operation of the cell. Various approaches are implemented with different types of circuits coupled to detect the impedance values of the respective cells.
Type:
Grant
Filed:
July 23, 2012
Date of Patent:
May 19, 2015
Assignee:
DATANG NXP SEMICONDUCTORS CO., LTD.
Inventors:
Johannes van Lammeren, Matheus Johannus Gerardus Lammers
Abstract: Consistent with an example embodiment, there is an apparatus comprising a carrier, a laminated battery provided on a major surface of the carrier, and an integrated circuit. The laminated battery includes a bottom electrode layer, an electrolyte layer, and a top electrode layer. The integrated circuit is connected to the bottom electrode layer and the top electrode layer. The integrated circuit is surrounded by the laminated battery on the major surface of the carrier.
Type:
Grant
Filed:
November 24, 2010
Date of Patent:
May 19, 2015
Assignee:
NXP B.V.
Inventors:
Romano Hoofman, Coen Tak, Marc Andre De Samber
Abstract: A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.
Type:
Grant
Filed:
April 5, 2008
Date of Patent:
May 19, 2015
Assignee:
NXP, B.V.
Inventors:
Matthias Merz, Youri V. Ponomarev, Gilberto Curatola