Patents Assigned to Oki Semiconductor Co., Ltd.
  • Patent number: 8860204
    Abstract: There is provided a semiconductor device including: plural bit cells each including the same circuit; plural electrodes supplied with power from outside, wherein each of the respective plural electrodes is mounted above the same circuit within the plural bit cells. Further, there is provided a semiconductor package including: the semiconductor device; a substrate mounted with the semiconductor device; an external input terminal formed on the substrate; an external output terminal formed on the substrate; an input wiring pattern connecting the semiconductor device mounted above the substrate and the external input terminal; an output wiring pattern connecting the semiconductor device mounted above the substrate and the external output terminal; and plural power supply lines, arranged without contact with each other on the same face of the substrate, and connecting the plural electrodes mounted to the semiconductor device to the corresponding electrode from the plural external power input electrodes.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: October 14, 2014
    Assignee: OKI Semiconductor Co., Ltd.
    Inventor: Koji Higuchi
  • Patent number: 8804882
    Abstract: Suitable gain control is achieved at low cost. In a receiving apparatus, an RF signal that is amplified by an RF amp is converted to an IF frequency by a frequency conversion unit and amplified by an IF amp, then the output signal from the IF amp that was converted to a digital signal by an ADC is inputted to a digital processing unit. The output from the ADC is then filtered to a desired frequency by a digital filter and inputted to the digital processing unit. In the digital processing unit the signal power before filtering by the digital filter and the signal power after filtering by the digital filter are measured, and the power difference is calculated. Based on the power difference, which indicates the ratio of unnecessary power, the digital processing unit controls the gain ratio of the RF amp and IF amp.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: August 12, 2014
    Assignees: Casio Computer Co., Ltd., Oki Semiconductor Co., Ltd.
    Inventors: Hiromune Nagai, Shinpei Matsuda, Hiroji Akahori
  • Patent number: 8786289
    Abstract: A semiconductor device for monitoring batteries or cells connected in series has a selector switch that selects one of the batteries or cells and outputs voltages obtained from its positive and negative terminals. A pair of buffer amplifiers receives these voltages at high-impedance input terminals and output corresponding voltages to a level shifter. The level shifter generates an output voltage equal to the difference between the outputs of the buffer amplifiers. By preventing current flow between the selector switch and the level shifter, the buffer amplifiers reduce the output droop that occurs at the beginning of a voltage measurement, even if the semiconductor device is connected to the batteries or cells through a low-pass filter circuit with a comparatively large time constant. Measurement time is shortened accordingly.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 22, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masaru Sekiguchi
  • Patent number: 8786087
    Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which includes a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem where the material of the first main interconnection transfers from a portion connected to the second interconnection due to electromigration to form a void, with the result that the first interconnection is disconnected from the second interconnection.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: July 22, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yusuke Harada
  • Patent number: 8749291
    Abstract: A semiconductor integrated circuit has an output terminal connected to an external load, an internal signal line by which the output terminal is connected to an internal node, and a voltage generator that outputs a voltage to the internal node, for output through the internal signal line and the output terminal to the external load. A voltage attenuating element is connected to the internal signal line to attenuate voltage swings on the internal signal line. A limiting circuit is connected to the internal node to limit the voltage at the internal node to a predetermined range. Moderate voltage swings caused by external electromagnetic interference are kept within the predetermined range by the voltage attenuating element, so that the limiting circuit does not operate and the average output voltage is not changed.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: June 10, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Masakuni Kawagoe, Shoji Nitawaki, Chikashi Fuchigami
  • Patent number: 8736320
    Abstract: A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: May 27, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yukio Kawamura
  • Patent number: 8736595
    Abstract: A display driving device and method capable of canceling an offset voltage while suppressing a delay in outputting an image signal to the display device by the time required for the image signal to be completely received in the display device. In an exemplary embodiment, when an image signal is input to an operational amplifier, a pixel of the display device, to which a voltage based on the image signal is applied, and an output terminal of the operational amplifier are connected to each other. The image signal is input to the operational amplifier, and, when charges corresponding to an offset voltage generated in the operational amplifier have accumulated in a capacitor, the image signal is input to the operational amplifier together with the charges accumulated in the capacitor while the connection between the pixel and the output terminal of the operational amplifier is maintained.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: May 27, 2014
    Assignee: Oki Semiconductor Co., Ltd
    Inventor: Atsushi Hirama
  • Patent number: 8723303
    Abstract: An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip adjacent the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: May 13, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hidekazu Nasu, Satoshi Miyazaki
  • Patent number: 8698314
    Abstract: A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Nakayama
  • Patent number: 8692369
    Abstract: There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: April 8, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kikuo Utsuno
  • Patent number: 8692510
    Abstract: Disclosed is a battery charger including a battery cell, a reference voltage generating section, an A/D converting section including an A/D converter and a control section. The reference voltage generating section includes a first reference voltage circuit generating a first reference voltage and a second reference voltage circuit generating a second reference voltage equal to the first reference voltage. To diagnose the A/D converter, the first reference voltage circuit is used. To diagnose the first reference voltage circuit, a second A/D conversion value obtained by A/D converting a second divided voltage of the second reference voltage via the A/D converter using the first reference voltage is compared with a first reference value obtained by A/D converting a first divided voltage of the first reference voltage via the A/D converter using the first reference voltage when the first reference voltage circuit is normal.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 8, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yukihiro Kita
  • Patent number: 8692355
    Abstract: A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: April 8, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Daisuke Tanaka, Hiroyoshi Ichikura
  • Patent number: 8664666
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: March 4, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masamichi Ishihara
  • Patent number: 8664798
    Abstract: A semiconductor integrated circuit device includes a power supply circuit that generates one or more internal supply voltages from an external supply voltage, and one or more functional circuits that operate on the one or more internal supply voltages. A step-down converter in the power supply circuit generates one or more stepped-down voltages from the external supply voltage. A control circuit in the power supply circuit compares the external supply voltage with a reference voltage and selects the internal supply voltages from among the external supply voltage and the stepped-down voltages according to the result of the comparison. The semiconductor integrated circuit device can accordingly operate on different external power supplies, and can continue to operate on battery power even if the battery voltage drops.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: March 4, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Ken Nozaki
  • Patent number: 8665198
    Abstract: A source driver includes a ladder circuit for outputting multilevel gradation voltages by resistance voltage division, a first decoder for selecting one gradation voltage corresponding to the inputted image data to output the selected gradation voltage, an external power supply for supplying multilevel pre-charging voltages, a second decoder for selecting one pre-charging voltage corresponding to the image data, an operational amplifier for outputting the driving voltage corresponding to the inputted gradation voltage to the source electrode, a pre-charging switch interconnected between the operational amplifier and second decoder, and a controller for controlling the pre-charging switch. The connection between the first decoder and operational amplifier is always kept during the whole sampling period including a pre-charging period, and the controller controls the pre-charging switch to be turned on during the pre-charging period and turned off after the pre-charging period has expired.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 4, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Yoshinori Okada, Atsuhiro Miwata
  • Patent number: 8643161
    Abstract: A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: February 4, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hidenori Hasegawa
  • Patent number: 8633885
    Abstract: A display panel driving apparatus supplies pixel driving potentials corresponding to pixel data to the source lines of a display panel. The pixels are located at the intersections of the source lines and a set of scanning lines. For each pixel, the driving potentials are alternately positive and negative with respect to a common reference potential supplied to the display panel. While the display driving apparatus is latching the pixel data for the pixels on each scanning line, the output circuits of the display driving apparatus are disconnected from the source lines, allowing the source lines to return to the common reference potential, thereby avoiding unwanted current flows in the output circuits and unwanted distortion of the pixel driving waveforms.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: January 21, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Nakayama
  • Patent number: 8624555
    Abstract: A voltage monitoring system includes a plurality of voltage monitoring devices connected to each other in series for monitoring a voltage of each of battery units obtained by dividing per specific number a plurality of batteries connected in series. Each of the voltage monitoring devices includes a reception unit for receiving specific information transmitted from a former stage; a storage unit for storing the specific information received with the reception unit as self specific information; and a transmission unit for adding predetermined information to the specific information received with the reception unit, and for transmitting the specific information to a later stage as later stage specific information.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: January 7, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yoshihiro Murakami
  • Patent number: 8609527
    Abstract: A method of manufacturing a semiconductor device, includes: preparing a semiconductor IC chip and an external electrode terminal which is positioned away from the semiconductor IC chip, wherein the semiconductor IC chip has first and second electrode pads thereon, the second electrode pad being positioned between the first electrode pad and the external electrode terminal; connecting the first electrode pad and the external electrode terminal by a loop-like wire; and pressing a portion of the loop-like wire toward the semiconductor IC chip, thereby connecting the portion of the loop-like wire with the second electrode pad.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 17, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Isao Kurita
  • Patent number: 8604588
    Abstract: A semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: December 10, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Kenichiro Kusano, Junko Azami