Abstract: There is provided an oscillator circuit including: a current source; a resonant unit; an oscillation amplification unit connected to the current source while being connected in parallel to the resonant unit; a feedback resistor connected in parallel to the oscillation amplification unit; a bypass resistor having a resistance lower than a resistance of the feedback resistor; a switch unit connected between the feedback resistor and the bypass resistor, and configured to switch to the feedback resistor or the bypass resistor; and a control unit configured to control the switch unit such that a current from the current source is bypassed to the bypass resistor during a predetermined oscillation starting period, and to control the switch unit such that the current from the current source flows to the feedback resistor after the predetermined oscillation starting period has ended.

Abstract: A driving voltage output circuit for a matrix display panel includes high-side voltage followers and low-side voltage followers. Each voltage follower includes a differential input stage, a control stage, and an output stage. The differential input stage receives non-inverting and inverting inputs and produces first and second potentials. The control stage generates third and fourth potentials from the first and second potentials. The output stage includes three transistors connected respectively to the high-side power supply, the low-side power supply, and an intermediate reference potential, and connected in common to an output terminal. Two of the three transistors are of identical channel type and are controlled by the first and fourth potentials. The third transistor is of the opposite conductive type and is controlled by the third potential.

Abstract: An optical sensing device includes a silicon-on-insulator (SOI) substrate a semiconductor support substrate, an insulating layer located on the semiconductor support substrate, and a semiconductor layer located on the insulating layer. The optical sensing device further includes a visible light sensor located in the semiconductor support substrate, and an ultraviolet ray sensor located in the semiconductor layer.

Abstract: A semiconductor device including a first conduction type semiconductor layer; a second conduction type element forming region formed above the first conduction type semiconductor layer and formed with at least one semiconductor element formed on a surface region of the second conduction type element forming region; a first conduction type element-isolation region insulating and segregating the second conduction type element forming region from the exterior; and a second conduction type buried region formed at the interface of the first conduction type semiconductor layer and the second conduction type element forming region, formed separated from the first conduction type element-isolation region. In the semiconductor device a second conduction type high concentration region is buried in the surface of the second conduction type element forming region and formed to surround the semiconductor element and separated from the first conduction type element-isolation region.

Abstract: A photodiode includes a silicon semiconductor layer; a P-type high concentration diffusion layer with a P-type impurity diffused therein at a high concentration; an N-type high concentration diffusion layer with an N-type impurity diffused therein at a high concentration; and a low concentration diffusion layer with one of the P-type impurity and the N-type impurity diffused therein at a low concentration. The P-type high concentration diffusion layer and the N-type high concentration diffusion layer are formed in the silicon semiconductor layer, and are arranged to face each other with the low concentration diffusion layer in between. The photodiode further includes an interlayer insulation film formed on the silicon semiconductor layer, so that a covalent bond between silicon and hydrogen is formed in an atom row of the low concentration layer adjacent to an interface thereof with respect to the interlayer insulation film.

Abstract: A method of producing a Schottky diode includes the steps of: forming a resist layer on the semiconductor substrate; performing a first exposure process on the resist layer; performing a first developing process for developing the resist layer to form a first Schottky diode having an excess region; performing a first cleaning process; performing a second exposure process on the first Schottky diode; performing a second developing process on the first Schottky diode to remove the excess region from the first Schottky diode so that a second Schottky diode corresponding to the specific Schottky diode is formed; and performing a second cleaning process.

Abstract: A semiconductor device which is capable of preventing interface peeling and a crack from occurring in the vicinity of the edge part of a rewiring layer is provided. The semiconductor device includes a semiconductor substrate, an electrode pad formed on the semiconductor substrate, a first insulation film formed on the semiconductor substrate having a first aperture which exposes the electrode pad, a first conductor film formed on the electrode pad and the first insulation film, an external electrode electrically connected to the first conductor film, and a sealing resin which covers the first conductor film and the first insulation film. The first conductor film includes a plurality of copper layers which are stacked so that an outer edge portion of the first conductor film has a stepped portion.

Abstract: A camera module includes a sensor chip having a backside surface and a main surface including a sensor forming region and a sensor peripheral region surrounding the sensor forming region, in which a light receiving portion is disposed in the sensor forming region; a lens chip having a non-lens forming surface and a lens forming surface including a lens forming region and a lens peripheral region surrounding the lens forming region, in which a lens portion disposed in the lens forming region; a spacer portion for bonding the sensor peripheral region to the lens peripheral region with a specific space in between so that the light receiving portion faces the lens portion; and a cover including an opening portion for passing light from outside toward the lens portion and the light receiving portion.

Abstract: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 ? in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.

Abstract: A high-gain differential amplifier that is capable of high speed operation, outputs a signal representing a difference between signals respectively inputted to first and second input terminals and a phase-inverted signal thereof via first and second output terminals respectively. A first switching element making a short-circuit between the first input terminal and the second output terminal when turned on, a second switching element making a short-circuit between the second input terminal and the first output terminal when turned on, and a third switching element making a short-circuit between the first output terminal and the second output terminal when turned on are provided. The third switching element is turned on for a predetermined period while the first and second switching elements are turned off. Subsequently, the third switching element is switched off, and the first and second switching elements are switched on.

Abstract: A COF package in exemplary form includes a flexible base film, inner leads each made of metal and having a thickness d1, which are disposed at a peripheral edge of a semiconductor chip-mounted predetermined spot on the base film and protruded into the semiconductor chip-mounted predetermined spot, dummy patterns having a thickness d2 (<(d1+d3), where d3 is the thickness of the electrodes), which are disposed at predetermined positions within the semiconductor chip-mounted predetermined spot, a semiconductor chip, and an encapsulating resin. The semiconductor chip has a plurality of the electrodes each protruded into a main surface thereof and having the thickness d3. The electrodes are bonded to the inner leads respectively. Further, the encapsulating resin is charged between the base film and the semiconductor chip. The shape and/or position of the dummy patterns may mark the function of one or more inner leads.

Abstract: A method of producing a semiconductor device includes the steps of preparing an SOQ (Silicon On Quartz) substrate in which a semiconductor layer is formed on a quartz substrate; forming a plurality of semiconductor device forming regions in the SOQ substrate; forming a crack inspection pattern in the SOQ substrate; inspecting the crack inspection pattern to detect a crack in the crack inspection pattern in a first inspection step; and inspecting the semiconductor device forming regions to detect a crack in the semiconductor device forming regions in a second inspection step when the crack is detected in the crack inspection pattern in the first inspection step.

Abstract: A wafer of semiconductor integrated circuits with wafer-level chip-scale packages is tested in two stages. The chip-scale packages include conductive posts extending through a sealing layer and capped by terminals. Measurements strongly affected by contact resistance are carried out before the terminals are formed, using a first probe card having probe pins that contact the ends of the conductive posts. Other measurements are carried out after the terminals are formed, using a second probe card having probe pins that contact the terminals. Accurate measurements can be made in this way even if the terminals are lead-free solder bumps with variable contact resistance. Fabrication yields are improved accordingly.

Abstract: There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input.

Abstract: A method of manufacturing a semiconductor device having a process for cleaning a semiconductor substrate after the semiconductor substrate is etched for patterning includes a first process of preparing the semiconductor substrate having a first temperature, a second process of setting the semiconductor substrate at a second temperature, a third process of etching the semiconductor substrate having the second temperature by etching liquid having a third temperature, a fourth process of cleaning the semiconductor substrate to which the etching liquid is adhered, by ultrapure water having a fourth temperature, wherein the second temperature is set at the range between the first and the third temperatures.

Abstract: A test element group (TEG) pattern formed of two wiring patterns alternately disposed in a swirl configuration is used for testing an insulation property of a wafer-level chip scale package (WL-CSP) having a micro wiring such as an inductor element. The insulation property of the WL-CSP can be monitored with enhanced accuracy by measuring a resistance value between solder terminals electrically connected to the swirl-shaped TEG pattern.

Abstract: There is provided a start-up circuit of an internal power supply of a semiconductor memory, including: an odd number of inverters that are connected in series and output a signal indicating whether or not to start to supply power from an internal power supply circuit of the semiconductor memory to an internal power supply circuit, and a discharge unit that is connected to an output side of an inverter at an odd-numbered stage and discharges charges remaining at the connection point between the inverter at the odd-numbered stage and the inverter at the stage immediately thereafter, after supply of power to operate the inverters is stopped.

Abstract: There is provided a semiconductor non-volatile memory including: plural memory sections, a voltage application section, and a control section that controls the voltage application section wherein the control section controlling voltage application such that, based on a value of current detected by a current detection section, in a region where the current flowing in a channel region is greater than a predetermined target value at which a amount of charge accumulated has become a specific value in at least one of a first charge accumulating section or a second charge accumulating section, when a value of current flowing in the channel region approaches a target value, a rate of increase in the charge accumulating amount per time is decreased at least once.

Abstract: Provided are a semiconductor manufacturing apparatus and method, capable of reliably and rapidly transporting a heated semiconductor wafer. the apparatus is provided for transporting a semiconductor wafer, which has been processed by desired treatment (for example, film formation) and is held by a susceptor equipped with a heater, to the outside by a transport arm which holds the semiconductor wafer by suction, by moving the susceptor to a certain position above a top of a wafer waiting stage and introducing the semiconductor wafer held by the susceptor onto the top of the wafer waiting stage. Then, the susceptor present on the top of the wafer waiting stage is moved in a horizontal direction. After a certain cooling time, the transport arm holds the semiconductor wafer placed on the wafer waiting stage by suction and transports the semiconductor wafer to outside.

Abstract: A constant-voltage power supply circuit which limits the consumption current inside at startup or when overloaded and suppresses the occurrence of an overshoot at startup, comprises an error amplifying part; an output part having an outputting PMOS; a load current monitoring part that monitors a load current flowing through the PMOS and increases the bias current of the error amplifying part according to the load current; and a gain adjusting part having a current limiting resistor and that monitors the load current and decreases a gain of the error amplifying part according to this load current. Hence, at startup or when overloaded, the gain adjusting part operates as a limiter circuit. Hence, at startup or when overloaded, the consumption current inside can be limited. Further, at startup, the response is made slower by this limiter operation, thus suppressing the occurrence of an overshoot.