Abstract: In a smartphone that outputs PCM data and DSD data of different data format from PCM data to a USB DAC, to prevent generation of noises from the USB DAC when the smartphone accepts stopping instruction of outputting digital audio data to the USB DAC while outputting DSD data to the USB DAC. A controller 11 outputs mute data representing silence of DSD data to a USB DAC 2 when it accepts pausing instruction while outputting DSD data to the USB DAC 2.

Abstract: It is an object of the present invention to provide an audio having intended sound quality to a user even when a headphone that is different from a headphone used for generating equalizer information is used. A correcting section corrects equalizer curve stored in an equalizer curve storage section based on a correction curve that is a gain difference of a frequency characteristic between a first headphone and a second headphone when the second headphone the frequency characteristic of which is different from that of the first headphone is used so as to output the corrected equalizer curve to a reproducing section. The reproducing section executes an equalizing process based on the equalizer curve output from the correcting section.

Abstract: Restoration data is enabled to be written into a nonvolatile memory according to a simple process without using large capacity of a volatile memory. An SRAM writing section sets an updating request flag in a non-delay updating request flag region corresponding to a non-delay region where the restoration data is written. When the updating request flag is set in the non-delay updating request flag region, an EEPROM writing section writes the restoration data stored in the non-delay region corresponding to the non-delay updating request flag region into an EEPROM.

Abstract: There is provided a ?? modulator including a loop filter for inputting an m-value digital signal into a subtractor, an n-value quantizer for inputting a first output signal to be output from the loop filter and outputting a second output signal as an n-value digital signal, and a selecting device for inputting the first output signal and the second output signal therein, feeding back the first output signal to a subtractor of the loop filter when an absolute value of the first output signal is a predetermined value or more, and feeding back the second output signal to the subtractor of the loop filter when the absolute value is less than a predetermined value. The predetermined value in the selecting device is set to be larger than a maximum value of an absolute value of a quantization value to be obtained by the n-value digital signal.

Abstract: A signal modulation circuit includes a feedback circuit configured to generate the feedback signal for feeding back a drive signal from a driver circuit to an input signal. The feedback circuit includes at least first and second resistors connected together in series, the second resistor having a higher resistance value than that of the first resistor. One end of the first resistor is connected to a subtracter, and one end of the second resistor is connected to the driver circuit. A first line distance as the line length between one end of the first resistor and the subtracter and a second line distance as the line length between one end of the second resistor and the driver circuit are set shorter than a third line distance as the line length between the other end of the first resistor and the other end of the second resistor.

Abstract: There is provided an input device that needs not to change processing of means (a key processor or a key processing microcomputer as a software module) for performing processing based on an on or off state of a key switch in a matrix system and an A/D system. A key-in microcomputer detects the on or off states of plural key switches K based on voltages at A/D input terminals. The key-in microcomputer converts the detected on or off states of the plural key switches K into a bit array. A key processing microcomputer performs the processing based on the bit array converted by the key-in microcomputer.

Abstract: To realize a change in a volume that does not give a user a feeling of strangeness even when a great processing load is put on a volume determining unit. A volume controller performs a process for determining a new volume of an audio signal based on an alternate pulse interval that is based on a counting time and the number of pulses counted by a counting section within the counting time and a current volume stored in a storage section, and storing the determined new volume as the current volume in the storage section, the same number of times as the number of pulses counted by the counting section every counting time, and outputs last information stored as the current volume in the storage section to an electronic volume.

Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.

Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.

Abstract: A volume control system, that can easily check current volume values with respect to volume values settable in a plurality of audio output devices when a volume value representing the volume values of the audio output devices is displayed, is provided. A controller of the volume control system can be connected to the plurality of the audio output devices, and can control the audio output devices. The controller obtains the volume values of the audio output devices and predetermined upper limit volume values stored in the audio output devices, and displays percentages of the volume values with respect to the predetermined upper limit volume values as total volume values. Further, the controller displays values that are determined by multiplying the total volume values and percentages of the predetermined upper limit volume values with respect to prescribed values as the volume values of the audio output devices.

Abstract: An amplifying device is provided that reduces power consumption and quickly starts amplification of an audio signal of a channel to be used. A control section 17 inputs a control signal for instructing operation or standby into post-amplifying sections 11b and 12b, and inputs a control signal for instructing standby to post-amplifying sections 13b and 14b. In the post-amplifying section 11b, when the control signal for instructing standby or operation is input from the control section 17, a modulation circuit 52 modulates the analog audio signal into a switching signal. An output stage circuit 54 amplifies the output signal. When the control signal for instructing the operation is input from the control section 17, a driving circuit 53 drives the output stage circuit 54 in response to the switching signal, and stops the driving of the output stage circuit 54 when the control signal for instructing standby is input.

Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.

Abstract: In a music reproducing apparatus for converting audio data into audio data of different data format so as to reproduce it, gapless reproduction and cross-fade reproduction are performed in a switching manner, and generation of a noise at time of the gapless reproduction is repressed. When a reproducing section performs the gapless reproduction, a converting section performs conversion into PCM data to be reproduced latterly using a buffer used for conversion into the PCM data to be reproduced formerly. Further, when the reproducing section performs the cross-fade reproduction, the converting section generates a buffer different from the buffer used for the conversion into the PCM data to be reproduced formerly in a storage section, and performs the conversion into the PCM data to be reproduced latterly using the generated buffer.

Abstract: When the instruction for increasing the volume level is input by the user's operation and the signal representing the set value or more is output from a detector, a controller does not increase the volume levels of the first volume controller and the second volume controller. When the signal representing the set value or more is not output from the detector and the second volume level has a predetermined value, the controller increases the first volume level. When the signal representing the set value or more is not output from the detector and the second volume level is less than the predetermined value, the controller increases the second volume level.

Abstract: An audio processing section generates at least a left-front audio signal, a right-front audio signal, a second left audio signal that is the same as a left-front audio signal, and a second right audio signal that is the same as the right-front audio signal based on a left-front audio signal and a right-front audio signal supplied from an audio selector, and outputs these signals to a main output terminal, and supplies the second left audio signal and the second right audio signal also to a switch section. When a first mode is selected, the switch section selects the audio signal from the audio processing section, and supplies it to a ZONE2 output terminal. On the other hand, when modes other than the first mode are selected, the switch section selects an audio signal from the audio selector, and supplies the selected audio signal to the ZONE2 output terminal.

Abstract: A frequency characteristics determination device that can prevent generation of a frequency response curve having an unnatural shape is provided. A CPU 11 sets pass points Pi and Pi+1 through which the frequency response curve of an audio signal should pass. Pi+1 of a frequency Xpi+1 which is higher than a frequency Xpi of the pass point Pi. The CPU 11 determines a direction point ai of a Bezier curve Ci for connecting the pass points Pi and Pi+1 based on the pass points Pi and Pi+1. The CPU 11 determines whether a frequency Xai of the direction point ai is within a reference range between not less than the frequency Xpi and not more than the frequency Xpi+1. When the frequency Xai is out of the reference range, the CPU 11 moves the direction point ai so that the frequency Xai is within the reference range.

Abstract: An aspect of the present invention provides a transmitting apparatus that reduces a transmission delay of content data in transmitting the content data transmitted from a source device to a receiving apparatus. A first repeater device is a transmitting apparatus in conformity to a Wireless HD. A BD player is in conformity to an HDMI. The first repeater device receives uncompressed content data transmitted from the BD player. Before receiving the content data from the BD player, the first repeater device performs authentication processing between the BD player and the first repeater device based on an HDCP. Before the authentication processing is ended, the first repeater device starts processing of establishing a communication channel from the first repeater device to a second repeater device using an LRP. The first repeater device transmits the content data transmitted from the BD player to the second repeater device through the established communication channel.

Abstract: A pre-out terminal that outputs the audio signal is fixed. One of a surround back left audio signal SBL, a left outside audio signal LW, and a left upside audio signal LH is selected by a user operation, and output to a pre-out terminal 11c. A determination which one of two signals except the pre-out terminal in the signals SBL, LW, and LH is included in multichannel audio data is made. When it is determined that the signal SBL is included, the signal SBL amplified by an amplifier 12a is supplied to an SBL speaker terminal 14a. When it is determined that the signal LW is included, the signal LW amplified by the amplifier 12a is supplied to an LW speaker terminal 14b. When it is determined that the signal LH is included, the signal LH amplified by the amplifier 12a is supplied to an LH speaker terminal 14c.