Abstract: A data writing apparatus includes a tape drive, a buffer and non-volatile memory. When a synchronization request is received from a device sending data to be written to a tape, the apparatus is operable to copy data corresponding to the synchronization request from the buffer to the non-volatile memory. The data may be stored in the non-volatile memory until at least the time when the data which it is a copy of is written to the tape from the buffer.

Abstract: An optical connector is described. This optical connector spatially segregates optical coupling between an optical fiber and an optical component, which relaxes the associated mechanical-alignment requirements. In particular, the optical connector includes an optical spreader component disposed on a substrate. This optical spreader component is optically coupled to the optical fiber at a first coupling region, and is configured to optically couple to the optical component at a second coupling region that is at a different location on the substrate than the first coupling region. Moreover, the first coupling region and the second coupling region are optically coupled by an optical waveguide.

Abstract: A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing unit processes the variable vector processing instructions using the appropriate vector register with the instructions having the same width as the appropriate vector register. The width that the processing unit obtains may be less than an actual width of the appropriate vector register and may set by the processing unit. In this way, many different vector widths can be supported using a single set of instructions for vector processing. New instructions are not required if vector widths are changed and processing units having vector registers of differing widths do not require different code.

Abstract: A method for memory protection in a multiprocessor system, involving receiving a request at a first carrier to perform a memory operation at a memory address, wherein the first carrier receives the request from a processor, determining by the first carrier whether the processor is permitted to access memory at the memory address using a carrier identification (ID) of a second carrier, wherein the second carrier is associated with a memory controller used to access the memory, and sending the request to the second carrier, if the processor is permitted to access the memory.

Abstract: A computer system to schedule loads across a set of processor cores is described. During operation, the computer system receives a process to be executed. Next, the computer system obtains one or more thermodynamic process characteristics associated with the process and one or more thermodynamic processor-core characteristics associated with operation of the set of processor cores. Then, the computer system schedules the process to be executed by at least one of the processor cores based on the one or more thermodynamic process characteristics and the one or more thermodynamic processor-core characteristics.

Abstract: Improved performance of a chip multithreading (CMT) processor during processing of a cipher is disclosed. The chip multithreading processor may be located on a chip multithreading processor chip that includes a processor cache. The selection of a cipher is received. The cipher is processed by executing a plurality of cryptographic operations on the chip multithreading processor. Lookup tables used during the execution of the plurality of cryptographic operations are determined. The size of at least one of the lookup tables may be increased, such that the at least one lookup table is able to be stored in a processor cache located on the chip multithreading processor chip. Further adjustments may be made to the size of one or more lookup tables depending on the cipher selected, other operations executing on the chip multithreading processor, or both.

Abstract: The invention relates to a system that includes a file system configured to create a snapshot of a hierarchical block tree (HBT) and a storage pool. After the snapshot has been created, the storage pool includes a snapshot, where the snapshot includes a copy of a first version of a root block and the HBT, where the HBT includes a second version of the root block. Further, the copy of the first version of the root block is created prior to overwriting the first version of the root block with the second version of the root block, the second version of the root block comprises references to a first block and a second block, and the copy of the first version of the root block comprises a reference to the first block and no reference to the second block.

Abstract: Methods and apparatus for processing a network connection in a computer system including a software network protocol stack and a network interface card including a hardware network protocol stack are disclosed. State information associated with the network connection is provided to or received by the driver associated with the network interface card. The driver provides the state information to the network interface card, thereby enabling the network interface card to process the network connection. In addition, any packet that is processed by the network interface card is also provided to the driver. Since the driver can maintain a copy of the state information and a copy of the data packet, the software network protocol stack can obtain the state information and the data packet from the driver in the event of a failure of the network interface card.

Abstract: Provided is a method, which may be performed on a computer, for prefetching data over an interface. The method may include receiving a first data prefetch request for first data of a first data size stored at a first physical address corresponding to a first virtual address. The first data prefetch request may include second data specifying the first virtual address and third data specifying the first data size. The first virtual address and the first data size may define a first virtual address range. The method may also include converting the first data prefetch request into a first data retrieval request. To convert the first data prefetch request into a first data retrieval request the first virtual address specified by the second data may be translated into the first physical address. The method may further include issuing the first data retrieval request at the interface, receiving the first data at the interface and storing at least a portion of the received first data in a cache.

Abstract: One embodiment provides a system that analyzes a target electromagnetic signal radiating from a monitored system. During operation, the system monitors the target electromagnetic signal using a near-isotropic antenna that includes a set of receiving surfaces arranged in a regular polyhedron. Next, the system obtains a set of received target electromagnetic signals from the receiving surfaces. Finally, the system assesses the integrity of the monitored system by separately analyzing each of the received target electromagnetic signals.

Abstract: A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction.

Abstract: A method for managing a security lifecycle of a federated web service provider (WSP) is described. The method includes populating a graphical user interface with available security mechanisms, receiving a selection of a selected security mechanism from a user, and creating a deployment time policy generator for instantiating the selected security mechanism in outgoing messages generated by the WSP. A system and machine readable-medium for a deployment tool for performing the method are also described.

Abstract: A method for generating authentication code for web service resources. The method includes receiving a selection of a resource method, where the resource method defines a method for interacting with a resource associated with a web service. The method further includes determining an authentication scheme for the resource method, where the authentication scheme defines an authentication mechanism required during execution of the resource method to enable interaction with the resource. The method further includes generating authentication code for the resource method using the authentication scheme, where the authentication code enables a user executing the resource method to interact with the resource.

Abstract: An interface device for a compute node in a computer cluster which performs Message Passing Interface (MPI) header matching using parallel matching units. The interface device comprises a memory that stores posted receive queues and unexpected queues. The posted receive queues store receive requests from a process executing on the compute node. The unexpected queues store headers of send requests (e.g., from other compute nodes) that do not have a matching receive request in the posted receive queues. The interface device also comprises a plurality of hardware pipelined matcher units. The matcher units perform header matching to determine if a header in the send request matches any headers in any of the plurality of posted receive queues. Matcher units perform the header matching in parallel. In other words, the plural matching units are configured to search the memory concurrently to perform header matching.

Abstract: A thread scheduling technique for assigning multiple threads on a single integrated circuit is dependent on the CPIs of the threads. The technique attempts to balance, to the extent possible, the loads among the processing cores by assigning threads of relatively long-latency (low CPIs) with threads of relatively short-latency (high CPIs) to the same processing core.

Abstract: A method for delivering a data stream to a plurality of clients in a network. The method involves receiving the data stream from a media server, where the data stream includes a plurality of data packets and a data stream identifier associated with at least one of the plurality of data packets, securing the data stream received from the media server by applying a filter to the data stream to obtain a filtered data packet from the plurality of data packets based on the data stream identifier, encrypting the filtered data packet using an encryption scheme to obtain a encrypted media content, and distributing the encrypted media content to at least one of the plurality of clients in the network.

Abstract: A network communication system and method providing a communication protocol extension for direct memory access operations allowing the separation of the command and data paths. The identification of the communication path to a third-party device is provided to a direct-memory-access initiator allowing the passing of data directly to the third-party device.

Abstract: A system and method for concurrency control may use slotted read-write locks. A slotted read-write lock is a lock data structure associated with a shared memory area, wherein the slotted read-write lock indicates whether any thread has a read-lock and/or a write-lock for the shared memory area. Multiple threads may concurrently have the read-lock but only one thread can have the write-lock at any given time. The slotted read-write lock comprises multiple slots, each associated with a single thread. To acquire the slotted read-write lock for reading, a thread assigned to a slot performs a store operation to the slot and then attempts to determine that no other thread holds the slotted read-write lock for writing. To acquire the slotted read-write lock for writing, a thread assigned to a slot sets its write-bit and then attempts to determine that the write-lock is not held.

Abstract: Some embodiments of the present invention provide a system that computes a target secret St in a sequence of secrets S0 . . . Sn. During operation, the system obtains k hash functions h1, . . . , hk, where h1 is known as the “lowest order hash function”, and hk is known as the “highest order hash function.” Associated with each hash function hi is a seed value seed comprising a pair (seedindexi, seedvaluei). Hash function hi operates on a pair (indexi, valuei) to produce a pair (newindexi, newvaluei), where newindexi>indexi. To compute target secret St, the hash functions are applied successively, starting with the highest order hash function whose associated seed's index value is largest without being greater than t, applying that hash function as many times as possible without having that hash function's output's index value become greater than t, and then applying each successive hash function in turn as many times as possible, until St has been computed.

Abstract: A system and method for automatically determining whether a newer version of an application programming interface (API) is backwards compatible with an older version is disclosed. The method includes comparing the two versions of the API to determine a set of atomic differences between the two versions and applying a set of backwards compatibility rules to the set of atomic differences. For each atomic difference, applying the rules includes analyzing the atomic difference to determine any applicable backwards compatibility rules and evaluating each applicable rule for the atomic difference to determine whether the atomic difference represents a violation. The method also includes storing an indication of any backwards compatibility violations from the evaluation.