Abstract: A method for fault management. The method includes generating, in firmware of a computer system, a physical resource inventory (PRI) of a plurality of hardware components of the computer system, wherein the PRI defines a hierarchy of the hardware components. The method further includes traversing, by an enumerator executing in a fault manager, the PRI to generate a topology of the plurality of hardware components. The topology is used for fault management of the computer system.

Abstract: A reader-writer lock is provided that scales to accommodate multiple readers without contention. The lock comprises a hierarchical C-SNZI (Conditioned Scalable Non-Zero Indicator) structure that scales with the number readers seeking simultaneous acquisition of the lock. All readers that have joined the C-SNZI structure share concurrent acquisition, and additional readers may continue to join until the structure is disabled. The lock may be disabled by a writer, at which time subsequent readers will wait (e.g., in a wait queue) until the lock is again available. The C-SNZI structure may be implemented in a lockword or in reader entries within a wait queue. If implemented in reader entries of a wait queue, the lockword may be omitted, and new readers arriving at the queue may be able join an existing reader entry even if the reader entry is not at the tail of the queue.

Abstract: A method for providing a lightweight grid computing environment. The method includes providing a web server running on a computer device and a grid engine on the web server that is adapted for processing grid compute requests from user programs. The grid engine receives a grid compute request from a user program that is processed by the grid engine to identify a client program available in the grid and a path in the grid to the client program. The method includes loading and running the client program with the grid engine to generate a client program output for transmittal to the user program. The grid compute request includes a URL request string including a name of the client program and the path to the client program and may also include a name of the computer device hosting the web server and a path to the grid engine.

Abstract: A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating with each register a symbolic expression selected from a set of possible symbolic expressions, locating an operation, if any, that is next within the sequence of operations and setting that operation to be a working operation, where the working operation has associated therewith a destination register and zero or more source registers, and processing the working operation when the working operation and any symbolic expressions of its source registers, if any, match at least one of a set of rules, where each rule specifies that the working operation must match a subset of the operation set, where each rule also specifies that the symbolic expressions, if any, of any source registers of the working operation must match a subset of the possible symbolic expressions, and where the rule also specifies a result, then posting the result as the symbolic expression of the destination

Abstract: A method and corresponding system for secure messaging between an edge application and internal business process. The method includes converting a client request in an object state into a network message, e.g., a markup language message, based on a data definition. A network connection is opened and the network message is transmitted from the edge application to a messaging application associated with the internal business processes, which maps the network message is mapped to one of the business processed based on the type of data object or object state of the network message. The network message is converted back to its original state using the data definition, and the converted network message is passed to the mapped business process for processing to create a response or response data object. The mapping step typically includes reading a configuration file that defines pairings between data object types and business objects.

Abstract: A scene manager, in response to detecting user input indicating an obscured window may initiate transparency assisted window focus and selection. The scene manager may cause the obscured window to be rendered fully opaque while causing any obscuring windows to be rendered highly, or at least partially, transparent allowing the contents of the obscured window to be at least partially visible through the transparent content of the obscuring windows. The scene manager may cause transparency-enabled applications to redraw obscuring windows to be highly transparent. Alternatively, the scene manager may utilize a graphics subsystem capable of rendering the obscuring windows highly transparent. The scene manager may be configured to cause obscuring windows to be rendered multiple times, each time with increasing levels of transparency so that the obscuring windows fade from opacity to transparency.

Abstract: A method for writing a data block to a storage pool. The method including receiving a write operation for a block, determining whether the block comprises metadata, and if the block comprises metadata: determining a first replication type for the block, and writing the block to the storage pool in accordance with the first replication type. If the block does not comprise metadata: determining a second replication type for the block and writing the block to the storage pool in accordance with the second replication type.

Abstract: A system performs operations comprising creating a call graph for a program translated from source code, identifying redundant exception handling code in the program utilizing the call graph, and removing the redundant exception handling code. The operation of identifying redundant exception handling code may comprise identifying at least one function or callsite by determining that a first function in the at least one function's or callsite's callee chain throws an exception and that the exception is handled by a second function in the function's or callsite's callee chain or by determining that an exception is not thrown in the at least one function's or callsite's callee chain. The operation of removing the redundant exception handling code may comprise removing redundant exception handling code included in at least one function or callsite and/or removing at least one entry for the at least one function or callsite from an exception lookup table.

Abstract: A computer system includes an integrated circuit that has a plurality of processing cores fabricated therein and configured to perform operations in parallel. Each processing core is configured to process multiple threads, where a thread is assigned to one of the plurality of processing cores dependent on a cache hit rate of the thread.

Abstract: An input of a layout of one or more components in a container component is received and a new cross platform layout of the one or more components in the container component is generated. The cross platform layout includes at least one automatically sized autopad and/or container autopad that defines spacing to properly position the one or more components within the container component. The size of the autopad and/or container autopad is determined upon execution of the cross platform layout on a software platform using a visual guideline for that software platform. In some embodiments, some or all of the components are automatically positioned in the cross platform layout such that a contents of each of the components, such as text, is laid out within the container component along the same baseline.

Abstract: Embodiments of a method for determining locations of computers in a group of computers, which may be performed by a system, are described. During operation, the system receives a location of a first computer in the group of computers. Then, the system determines locations of one or more additional computers in the group of computers relative to the first computer based on vibration spectra associated with the first computer and the one or more additional computers.

Abstract: A multi-chip module (MCM) is described. This MCM includes two substrates, having facing surfaces, which are mechanically coupled. Disposed on a surface of a first of these substrates, there is a negative feature, which is recessed below this surface. A positive feature in the MCM, which includes an assembly material other than a bulk material in the substrates, at least in part mates with the negative feature. For example, the positive feature may be disposed on the surface of the other substrate. Alternatively, prior to assembly of the MCM, the positive feature may be a separate component from the substrates (such as a micro-sphere). Note that the assembly material has a bulk modulus that is less than a bulk modulus of the material in the substrates. Furthermore, at least a portion of the positive feature may have been sacrificed when the mechanical coupling was established.

Abstract: Some embodiments provide systems and techniques for performing parameterizable cryptography. An encryption key can be determined based at least on a string associated with an authorization policy. The encryption key can then be used to encrypt information. The decryption key can also be determined based at least on the string associated with the authorization policy. Note that the authorization policy must be satisfied to decrypt information. In some embodiments, the systems and techniques for performing parameterizable cryptography are blindable. These blindable embodiments can be used to preserve privacy.

Abstract: Some embodiments of the present invention provide a system that detects the presence of constrained motion in one or more components in a computer system. First, a vibrational spectrum of the computer system is monitored while the computer system operates. Then, the vibrational spectrum is analyzed using a pattern-recognition model to detect constrained motion in one or more components in the computer system, wherein the pattern-recognition model classifies the vibrational spectrum as indicating constrained motion or as not indicating constrained motion.

Abstract: Some embodiments provide a system that facilitates concurrency control in a computer system. During operation, the system generates a set of signatures associated with memory accesses in the computer system. To generate the signatures, the system creates a set of hierarchical Bloom filters (HBFs) corresponding to the signatures, and populates the HBFs using addresses associated with the memory accesses. Next, the system compares the HBFs to detect a potential conflict associated with the memory accesses. Finally, the system manages concurrent execution in the computer system based on the detected potential conflict.

Abstract: Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.

Abstract: A system and method is provided to facilitate secure communications for a server-application executing on a resource-constrained device. A request, from a client application executing on a client device to access a server application executing on the resource-constrained device is received on an application-specific secure port of a resource-constrained device. The request is authenticated using a security token stored in an application context of the server application. The authentication is performed by a transport security layer protocol executing within the application context of the server application. The security token is specific for the server application. A secure connection is established directly between the secure port and the client application upon the authentication being successful.

Abstract: A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate.

Abstract: A system and method for performing efficient program instrumentation for memory profiling. A computing system comprises a memory profiler comprising a static binary instrumentation (SBI) tool and a dynamic binary analysis (DBA) tool. The profiler is configured to selectively instrument memory access operations of a software application. Instrumentation may be bypassed completely for an instruction if the instruction satisfies some predetermined conditions. Some sample conditions include the instruction accesses an address within a predetermined read-only area, the instruction accesses an address within a user-specified address range, and/or the instruction is a load instruction accessing a memory location determined from a data flow graph to store an initialized value.

Abstract: A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.