Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havin

Abstract: An integrated circuit chip, comprising: an electronic device; and a phase-change memory storing information of said electronic device. A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on said chip; storing information about said electronic circuit in said phase-change memory.

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract: A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract: A programmable resistance memory element using a conductive sidewall layer as the bottom electrode. The programmable resistance memory material deposited over the top edge of the bottom electrode, in a slot-like opening of a dielectric material. A method of making the opening.

Abstract: The semiconductor device comprising a chalcogenide phase change material. The chalcogenide material being programmed from one resistance state to another resistance state by applying a programming current to a resistor which is in thermal contact with the chalcogenide material. The semiconductor device may be used as memory element or as a programmable fuse.

Abstract: A memory element comprising a volume of phase change memory material; and first and second contact for supplying an electrical signal to the memory material, wherein the first contact comprises a conductive sidewall spacer. Alternately, the first contact may comprise a contact layer having an edge adjacent to the memory material.

Abstract: The invention relates to a phase-change memory device. The device includes a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode. Additionally, other isolated lower electrodes may be formed along a symmetry line that is orthogonal to the first two isolated lower electrodes. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation structure s around a memory cell structure diode stack.

Abstract: The method forms a phase change memory cell with a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction which is transverse to said first direction. The first and second thin portions are in direct electrical contact and define a contact area having sublithographic extent. The second thin portion is formed in a slit of sublithographic dimensions. According to a first solution, oxide spacer portions are formed in a lithographic opening, delimited by a mold layer. According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, the quantity of programmable material is minimized, and the programmable material that is reprogrammed from an amorphous to a crystalline state, and vice versa, is localized on a contact. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. A spacer is formed within the opening and a programmable material is formed within the opening such that the spacer reduces the programmable material on the contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

Abstract: An electrically operated programmable resistance memory element having a conductive layer as an electrical contact. The conductive layer has a raised portion extending from an edge of the layer to an end adjacent the memory material.

Abstract: A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration.

Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.

Abstract: The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction which is transverse to said first direction. The first and second thin portions are in direct electrical contact and define a contact area having sublithographic extent. The second thin portion is formed in a slit of sublithographic dimensions. According to a first solution, oxide spacer portions are formed in a lithographic opening, delimited by a mold layer. According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

Abstract: A method of making an electrically operated programmable resistance memory element. A sidewall spacer is used as a mask to form a raised portion of a conductive layer. A programmable resistance material is formed in electrical contact with the raised portion.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

Abstract: A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. The resistivity of the contact is modified by at least one of implanting ions into the contact, depositing a material on the contact, and treating the contact with plasma. In an aspect, a spacer is formed within the opening and programmable material is formed within the opening and on the modified contact. A conductor is formed on the programmable material and the contact transmits to a signal line.