Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

Abstract: Methods of programming a phase-change memory device that remedy device failure. The methods includes applying a sequence of two or more electrical energy pulses to the device, where the sequence of pulses includes positive polarity pulses and negative polarity pulses. In one method, two or more pulses of an initial polarity are applied and are followed by one or more pulses having opposite polarity. In another method, pulses of an initial polarity are repeatedly applied until the device fails and one or more pulses of opposite polarity are subsequently applied to restore the device to its initial performance. The pulses may be set pulses, reset pulses, or pulses that produce programmed states having a resistance intermediate between the set resistance and reset resistance of the device.

Abstract: A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.

Abstract: A programmable resistance memory element. The active volume of memory material is made small by the presence of a small area of contact between the conductive material and the memory material. The area of contact is created by forming a region of conductive material and an intersecting sidewall layer of the memory material. The region of conductive material is preferably a sidewall layer of conductive material.

Abstract: A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in a dielectric. The chalcogenic material and the storage region are part of a stack having a common etched edge.

Abstract: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.

Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

Abstract: An adjustable write pulse generator is disclosed. The adjustable write pulse generator includes a band-gap reference current, a programmable ring oscillator, a frequency divider and a single pulse generator. The band-gap reference current circuit generates a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory cell. The programmable ring oscillator generates a first set of continuous write “0” and write “1” pulse signals based on the well-compensated current. The frequency divider then divides the first set of continuous write “0” and write “1” pulse signals into a second set of continuous write “0” and write “1” pulse signals. The single pulse generator subsequently converts the second set of continuous write “0” and write “1” pulse signals into a single write “0” pulse signal or a single write “1” pulse signal when programming the chalcogenide memory cell.

Abstract: A multi-layer thin-film device includes thin film memory and thin film logic. The thin film memory may be programmable resistance memory, such as phase change memory, for example. The thin film logic may be complementary logic.

Abstract: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.

Abstract: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.

Abstract: A write circuit for providing distinctive write currents to a chalcogenide memory cell is disclosed. The write circuit includes a current amplitude trim module, a current amplification and distribution module, and a write current shaping module. The current amplitude trim module provides a well-compensated current across a predetermined range of temperatures, voltage supplies and process corners intended for programming a chalcogenide memory cell. The current amplification and distribution module amplifies the well-compensated current in order to meet a programming requirement of the chalcogenide memory cell. The write current shaping module supplies an appropriate amount of write “0” current or write “1” current, based on the amplified current, to program the chalcogenide memory cell accordingly.

Abstract: A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a substantially planar first area of electrical communication with the phase-change material. The radial memory device also includes a second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, the second area being laterally spacedly disposed from the first area and substantially circumscribing the first area. Further, a method of making a memory device is disclosed. The steps include depositing a first electrode, depositing a first insulator, configuring the first insulator to define a first opening. The first opening provides for a generally planar first contact of the first electrode.

Abstract: A memory includes a programmable resistance array with high ratio of dynamic range to drift coefficient phase change memory devices.

Abstract: A method of programming a multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where the active region includes two or more layers. The method includes providing an electrical signal between the two terminals, where the electrical signal alters an electrical characteristic of a layer remote from one of the terminals. In one embodiment, the layer remote from the terminal is a chalcogenide material and the electrical characteristic is resistance. In another embodiment, an electrical characteristic of the layer in contact with the terminal is also altered. The alteration of an electrical characteristic may be caused by a transformation of a chalcogenide material from one structural state to another structural state.

Abstract: A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer, within the opening, and over selected portions of the bottom electrode, and a top electrode layer deposited over the active material layer. The device uses temperature and pressure control methods to increase surface mobility in an active material layer, thus providing complete coverage or fill of the openings in the insulative layer, selected exposed portions of the bottom electrode layer, and the insulative layer.

Abstract: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.

Abstract: An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an analog memory access should be performed on a specific chalcogenide memory cell. The address and data control module allows a normal memory access to the chalcogenide memory cell according to an input address. The analog cell access and current monitoring module performs an analog memory access to the chalcogenide memory cell according to the input address, and monitors a reference current from a sense amplifier associated with the chalcogenide memory cell.

Abstract: A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.

Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.