Patents Assigned to PACT XPP Technologies AG
  • Patent number: 7581076
    Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: August 25, 2009
    Assignee: Pact XPP Technologies AG
    Inventor: Martin Vorbach
  • Patent number: 7577822
    Abstract: A reconfigurable processor (VPU) is designed for a technical environment having a standard processor (CPU) which has, for example, a DSP, RISC, CISC processor or a (micro)controller. The VPU and the CPU are coupled to form a processor-coprocessor arrangement. For the coupling, the CPU executes a program and provides, during the execution, configuration related information, in accordance with the configuration related information; a configuration load unit is instructed to load a configuration into the VPU and responsively loads the configuration into the VPU; the VPU processes data in accordance with the configuration; the CPU parallelly processes data by continuing the program execution if it can be continued without waiting for output of the VPU's data processing or, otherwise, executing a different program; and synchronization signals are transferred between the CPU and the VPU to synchronize the data processing of the VPU and CPU.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: August 18, 2009
    Assignee: Pact XPP Technologies AG
    Inventor: Martin Vorbach
  • Patent number: 7565525
    Abstract: A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: July 21, 2009
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 7480825
    Abstract: A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: January 20, 2009
    Assignee: Pact XPP Technologies AG
    Inventor: Martin Vorbach
  • Patent number: 7444531
    Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: October 28, 2008
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Volker Baumgarte
  • Patent number: 7434191
    Abstract: Configuration of a reconfigurable multidimensional field may include prioritizing required connections between cells, establishing connections having a high priority first, and establishing additional connections after the high priority connections have been established.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: October 7, 2008
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Daniel Bretz
  • Patent number: 7394284
    Abstract: A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: July 1, 2008
    Assignee: Pact XPP Technologies AG
    Inventor: Martin Vorbach
  • Patent number: 7337249
    Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: February 26, 2008
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Publication number: 20070299993
    Abstract: Procedures and methods for managing and transmitting data within multidimensional systems of transmitters and receivers are described. Splitting a data stream into a plurality of independent branches and subsequent merging of the individual branches to form a data stream is to be performable in a simple manner, the individual data streams being recombined in the correct sequence. This method is of importance in particular for executing reentrant code. The method is well suited, in particular, for configurable architectures; particular attention is paid to the efficient control of configuration and reconfiguration.
    Type: Application
    Filed: March 5, 2002
    Publication date: December 27, 2007
    Applicant: PACT XPP Technologies AG
    Inventors: Martin Vorbach, Volker Baumgarte, Armin Nuckel, Frank May
  • Patent number: 7266725
    Abstract: A method for efficiently debugging a program defining a plurality of configurations to be successively processed on a dynamically reconfigurable architecture including a plurality of logic elements cooperating with each other. The method includes storing data in a memory in a configuration-conforming manner, the data generated by executing a configuration forming part of the program on the reconfigurable architecture, and including algorithmically relevant state data of the program that is associated with at least one of the configurations. The method further includes subsequently continuing execution of the program, the execution including a reconfiguration, and detecting an error based on stored state data, wherein for each state for which corresponding state data is to be stored, the state remains unchanged at least until the corresponding state data is stored.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: September 4, 2007
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Frank May, Armin Nückel
  • Patent number: 7243175
    Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: July 10, 2007
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 7237087
    Abstract: An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded freely over a bus system, the EALU being decoupled from the bus system over input and output registers. The output registers are connected to the input of the EALU to permit serial operations. A bus control unit is responsible for the connection to the bus, which it connects according to the bus register. The unit is designed so that distribution of data to multiple receivers (broadcasting) is possible. A synchronization circuit controls the data exchange between multiple cells over the bus system. The EALU, the synchronization circuit, the bus control unit, and registers are designed so that a cell can be reconfigured on site independently of the cells surrounding it.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: June 26, 2007
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 7210129
    Abstract: A method for translating high-level languages to reconfigurable architectures is disclosed. The method includes building a finite automaton for calculation. The method further includes forming a combinational network of a plurality of individual functions in accordance with the structure of the finite automaton. The method further includes allocating a plurality of memories to the network for storing a plurality of operands and a plurality of results.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 24, 2007
    Assignee: PACT XPP Technologies AG
    Inventors: Frank May, Armin Nückel, Martin Vorbach
  • Patent number: 7174443
    Abstract: A method of run-time reconfiguration of a programmable unit is provided, the programmable unit including a plurality of reconfigurable function cells in a multidimensional arrangement. An event is detected. The source of the detected event is determined, and an address of an entry in a jump table is calculated as a function of the source of the event, the entry storing a memory address of a configuration for a reconfigurable function cell. The entry is retrieved and a state of a corresponding reconfigurable cell is determined. If the reconfigurable cell is in a reconfiguration state, the reconfigurable cell is reconfigured as a function of the configuration data. If the reconfigurable cell in not in reconfiguration state, the configuration data is stored in a FIFO.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: February 6, 2007
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 7036036
    Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: April 25, 2006
    Assignee: PACT XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 7028107
    Abstract: A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit is described. The system may include, for example, a configuration memory arranged between the functional elements and the higher-level unit; and a control unit configured to move at least one position pointer to a configuration memory location in response to at least one event reported by a functional element. At run time, a configuration word in the configuration memory pointed to by at least one of the position pointers is transferred to the functional element in order to perform reconfiguration without the configuration word being managed by a central logic.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: April 11, 2006
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 7010667
    Abstract: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: March 7, 2006
    Assignee: PACT XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 7003660
    Abstract: An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processing unit in accordance with the first configuration word. The method also includes transmitting a second configuration word to the first processing unit. The method also includes transmitting a reconfiguration signal to the first unit, the reconfiguration signal indicating that the first unit should begin processing data in accordance with the second configuration word. If the first processing unit has completed processing data in accordance with the first configuration word prior to when the reconfiguration signal is received by the first processing unit, data may be processed by the first processing unit in accordance with the second configuration word.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: February 21, 2006
    Assignee: PACT XPP Technologies AG
    Inventors: Martin Vorbach, Volker Baumgarte, Gerd Ehlers, Frank May, Armin Nückel
  • Patent number: 6990555
    Abstract: A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a group, and connecting the cache unit to a higher level unit via a tree structure. The cache unit may send requests for required commands to the higher level cache unit, which may return a command sequence including the required command, if the higher level cache unit holds the first command sequence including the required command in the higher level cache unit's local memory.
    Type: Grant
    Filed: January 24, 2004
    Date of Patent: January 24, 2006
    Assignee: PACT XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 6968452
    Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: November 22, 2005
    Assignee: PACT XPP Technologies AG
    Inventors: Martin Vorbach, Robert Münch