Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.

Abstract: A method of clocking a plurality of programmable, sequential data processing units, by adjusting the clock frequency of at least one of the programmable, sequential data processing units, without affecting the clock frequency of at least one other of the programmable, sequential data processing units.

Abstract: An array processor composed of processor cells that are programmed by a controlling unit, and that are reprogrammed when a cell has finished a current data processing operation, even while other cell continue to process data with their current programming.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies.

Abstract: A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory. The method includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the process results external memory.

Abstract: A bus system for transferring data between parts of a multiprocessor system. The bus system is divided into a plurality of segments. Each segment is controlled by a table providing routing information. The bus system establishes communication between a sender and a receiver according to data where the data includes an identifier that identifying the source of the data transfer and/or the target of the data transfer.

Abstract: An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.

Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A processor comprising an ALU a programmable function unit wherein the functional unit may be programmed to comprise multistage logic.

Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.

Abstract: An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.

Abstract: A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.

Abstract: A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.

Abstract: A plurality of stacked dies has outer dies that permits high heat dissipation. A plurality of processors is located on a first outer die. A plurality of memory elements located on a second outer die. An interconnect structure is located an inner die.

Abstract: A plurality of stacked dies has outer dies that permits high heat dissipation. A plurality of possessors is located on a first outer die. A plurality of memory elements located on a second outer die. An interconnect structure is located an inner die.

Abstract: A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.

Abstract: A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel.