Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: generating a first operation command via one of a plurality of processing circuits, wherein the first operation command instructs to access a first memory group in a plurality of memory groups; and in response to a first state information, sending a first command sequence to the first memory group according to the first operation command to instruct the first memory group to perform an access operation. The first state information reflects a first activation state of the plurality of memory groups, and the first command sequence does not include a control command sequence configured to activate the first memory group.

Abstract: A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.

Abstract: A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.

Abstract: A device control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: establishing a connection between the memory storage device and a host system; performing a first communication with the host system based on the connection and a first connection interface standard; performing a data recovery operation between the memory storage device and the host system via the connection during a period of performing the first communication; and switching to perform a second communication with the host system based on the connection and a second connection interface standard in a case that the data recovery operation is successfully performed, wherein the first connection interface standard is different from the second connection interface standard.

Abstract: A clock control circuit module, a memory storage device, and a clock control method are disclosed. The clock control circuit module is configured to: generate a clock signal; receive a first signal and the clock signal and sample the first signal according to the clock signal to generate a first sampling signal and a second sampling signal; obtain first position information corresponding to a first transition point of a first target signal and second position information corresponding to a second transition point of a second target signal according to the first sampling signal and the second sampling signal respectively; and evaluate a frequency shift status between the first signal and the clock signal according to the first position information and the second position information.

Abstract: A spread spectrum clock generator, a memory storage device, and a spread spectrum clock generation method are provided. The method includes: generating a spread spectrum clock signal according to a reference clock signal and a control signal; and adjusting the control signal to change a frequency of the spread spectrum clock signal based on multiple frequency change rates, wherein an initial frequency change rate of the spread spectrum clock is greater than a frequency change rate of the spread spectrum clock within a target time range.

Abstract: A memory operation method, a memory storage device, and a memory control circuit unit are disclosed. The memory operation includes following steps. First data is received from a host system. The first data is stored into a first physical unit which is mapped to a first logical unit. In a first operation mode, a target calculation is performed based on the first data and second data stored in a second physical unit to obtain third data, and the third data is different from the first data. The third data is stored into a third physical unit which is also mapped to the first logical unit. The third data is transmitted to the host system.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a state of the memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein the operation mode includes a first operation mode and a second operation mode, and a first waiting time before the memory storage device entering a power saving mode in the first operation mode is longer than a second waiting time before the memory storage device entering the power saving mode in the second operation mode.

Abstract: A clock control circuit, a memory storage device, and a clock control method are disclosed. The method includes: tracking a frequency of a first signal from a host system; generating, in a first mode, a clock signal according to the frequency of the first signal; and generating, in a second mode, the clock signal without reference to the frequency of the first signal.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method is described below. A read command sequence is transmitted, the read command sequence instructs to read a first physical unit, and the first physical unit belongs to a physical unit group. A first single-frame decoding is performed on a first data frame read from the first physical unit. First error evaluation information corresponding to the physical unit group is obtained in response to the first single-frame decoding being failed and a default condition not being satisfied. This default condition is used for triggering the multi-frame decoding on the physical unit group. A second single-frame decoding is performed on the first data frame according to the first error evaluation information.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: sending a first operation command sequence to a rewritable non-volatile memory module to instruct a first memory module in the rewritable non-volatile memory module to perform a first operation; obtaining a first time threshold value corresponding to the first operation; updating a first counting value corresponding to the first memory module; and sending a first query command sequence to the rewritable non-volatile memory module to query a status of the first memory module, in response to that the first counting value reaches the first time threshold value.

Abstract: A regulator circuit module, a memory storage device, and a voltage control method are disclosed. The method includes: generating an output voltage according to an input voltage by a driving circuit; generating a feedback voltage according to the output voltage; controlling the driving circuit to adjust the output voltage according to the feedback voltage by a regulator circuit; compensating an output of the regulator circuit by a compensating circuit; and activating or deactivating the compensating circuit according to an input bypass-voltage of a switch circuit.

Abstract: A data storage method, a host system, and a data storage system are disclosed. The method includes the following. An artificial intelligence (AI) model is executed. First data to be stored to a memory storage device is obtained. In response to the first data being generated by the AI model, second data is generated according to the first data, in which the second data includes the first data, and a data amount of the second data is greater than a data amount of the first data. A first write command is sent to the memory storage device according to the second data, so as to instruct the memory storage device to store the second data.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes establishing a connection between the memory storage device and a host system; receiving a first request from the host system via the connection; detecting a status of the memory storage device in a time range according to the first request; and determining whether to use a memory in the host system according to the status.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes establishing a connection between the memory storage device and a host system; receiving a first request from the host system via the connection; detecting a status of the memory storage device in a time range according to the first request; and determining whether to use a memory in the host system according to the status.

Abstract: A signature verification method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data, signature information, and first verification information from a memory storage device; performing a first verification operation according to the signature information and the first verification information; generating second verification information according to the first data; performing a second verification operation according to the first verification information and the second verification information; and performing a corresponding process on the first data according to an operation result of the first verification operation and an operation result of the second verification operation.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: in an initialization operation, setting a first physical unit to be operated in a first operation mode, and in the first operation mode, the first physical unit is programmed based on a first programming mode; receiving a plurality of commands, and the commands includes a first command and a second command, the first command instructs to store first data to a first logical unit, and the second command instructs to mark second data stored in a second logical unit as invalid data; and in response to that a target condition is satisfied, setting the first physical unit to be operated in a second operation mode, and in the second operation mode, the first physical unit is programmable based on a second programming mode.

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.

Abstract: A device control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: obtaining device status information of the memory storage device, and the device status information includes at least one of temperature information and power consumption information; and adjusting a connection interface standard adopted by a connection interface unit of the memory storage device from a first connection interface standard to a second connection interface standard according to the device status information, and the first connection interface standard is different from the second connection interface standard.