Patents Assigned to Phison Electronics Corp.
  • Publication number: 20240086109
    Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command from a host system, and the write command including first data; checking a status of a first physical programming unit in a first physical erasing unit; in response to the status of the first physical programming unit being a first status, sending a first command sequence to a rewritable non-volatile memory module, and the first command sequence being configured to instruct the rewritable non-volatile memory module to store at least part of the first data to the first physical programming unit.
    Type: Application
    Filed: October 17, 2022
    Publication date: March 14, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Yu-Chung Shen, Jia-Li Xu, Ping-Cheng Chen
  • Patent number: 11928358
    Abstract: A command management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: obtaining a plurality of commands from a memory of a host system; storing the commands in a first buffer region of the memory storage device; in response to a first command and a second command meeting a pairing condition in the first buffer region, putting the first command and the second command in the first buffer region in a first command queue of the memory storage device; and continuously executing the first command and the second command in the first command queue.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: March 12, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Hui Tseng
  • Patent number: 11907059
    Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 20, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11907529
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: February 20, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Sheng-Min Huang, Kuo-Hwa Ho, Shih-Ying Song
  • Patent number: 11886263
    Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 30, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Po-Jung Chou, Sheng-Wen Chen, Chung-Kuang Chen
  • Publication number: 20240031165
    Abstract: A signature verification method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data, signature information, and first verification information from a memory storage device; performing a first verification operation according to the signature information and the first verification information; generating second verification information according to the first data; performing a second verification operation according to the first verification information and the second verification information; and performing a corresponding process on the first data according to an operation result of the first verification operation and an operation result of the second verification operation.
    Type: Application
    Filed: August 1, 2022
    Publication date: January 25, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Aaron C Chuang, Meng-Chang Chen
  • Publication number: 20240020021
    Abstract: A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.
    Type: Application
    Filed: August 11, 2022
    Publication date: January 18, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Chia-Lung Ma, Zhen-Yu Weng
  • Publication number: 20240004554
    Abstract: A partial erasing management method, a memory storage device, and a memory control circuit unit are provided. The method includes: performing a first partial erasing operation on a first physical region among multiple physical regions in a first physical erasing unit to erase first data in the first physical region; after performing the first partial erasing operation on the first physical region, performing a first programming operation on the first physical region to store second data into the first physical region; and in response to at least one of the first partial erasing operation and the first programming operation, updating first status information related to the first physical region.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 4, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11853613
    Abstract: An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: December 26, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Bo Lun Huang
  • Patent number: 11843311
    Abstract: A switching power supply module and a memory storage device are disclosed. The switching power supply module includes a first voltage regulation circuit, a second voltage regulation circuit, a switch circuit and a control circuit. The first voltage regulation circuit is configured to regulate an original power as a first power. The second voltage regulation circuit is configured to regulate the original power as a second power. The control circuit is configured to control the switch circuit to conduct a first power supply path under a first status to provide the first power to the first power supply target. The control circuit is further configured to control the switch circuit to conduct a second power supply path under a second status to provide the second power to the second power supply target.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: December 12, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Shu-Han Chou
  • Patent number: 11829644
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.
    Type: Grant
    Filed: January 22, 2022
    Date of Patent: November 28, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Po-Cheng Su, Chih-Wei Wang, Yu-Cheng Hsu, Wei Lin
  • Patent number: 11816355
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes receiving first data from a host system; sending a first write command sequence instructing continuous writing of the first data to a plurality of first chip enabled (CE) regions in response to the memory storage device being in a first state; receiving second data from the host system; and sending a second write command sequence instructing continuous writing of the second data to at least one second CE region in response to the memory storage device being in a second state. A data amount of the first data is equal to a data amount of the second data. A total number of the first CE regions is greater than a total number of the at least one second CE region.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 14, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11809706
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: November 7, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Yu-Cheng Hsu, Tsai-Hao Kuo, Wei Lin, An-Cheng Liu
  • Patent number: 11797222
    Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: October 24, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Po-Cheng Su, Chih-Wei Wang, Wei Lin
  • Publication number: 20230297233
    Abstract: A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.
    Type: Application
    Filed: April 15, 2022
    Publication date: September 21, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20230297464
    Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.
    Type: Application
    Filed: April 7, 2022
    Publication date: September 21, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Publication number: 20230289102
    Abstract: An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.
    Type: Application
    Filed: April 20, 2022
    Publication date: September 14, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Bo Lun Huang
  • Patent number: 11757684
    Abstract: A retiming circuit module, a signal transmission system, and a signal transmission method are provided. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes built-in first signal transmission path and second signal transmission path. The multipath signal transmission circuit may perform first signal transmission between an upstream device and a downstream device based on a first signal transmission frequency and the second signal transmission path. During a period of performing the first signal transmission, the path control circuit may detect a first data sequence transmitted between the upstream device and the downstream device.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: September 12, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chun-Wei Chang, Ching-Jui Hsiao, Jen-Chu Wu, Yuwei Kuo
  • Patent number: 11755242
    Abstract: A data merging method can copy a new logical to physical mapping table and update a copied logical to physical mapping table according to a physical address of a recycling unit expected to be written at the same time. In this way, the number of times that the same logic to physical mapping table is read multiple times during the data merging operation can be reduced to improve the execution efficiency of the data merging operation, thereby increasing the system performance of the memory storage device.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: September 12, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Li Hsun Lien
  • Publication number: 20230283065
    Abstract: An over-voltage protection device, a memory storage device, and an over-voltage protection method are provided. The over-voltage protection device includes a main load switch, multiple power channels, a voltage detection circuit, and a control circuit. The main load switch is configured to receive power and provide the power to a first power channel among the power channels. The voltage detection circuit is configured to detect a power abnormal status of a second power channel among the power channels. The control circuit is configured to control the main load switch to stop power supply to the first power channel according to the power abnormal status.
    Type: Application
    Filed: March 30, 2022
    Publication date: September 7, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Shu-Han Chou