Abstract: A multiple-chip system and a timing synchronization method. The multiple-chip system includes multiple chips. The chips includes a first chip and at least one second chip. The chips are connected to each other through a same input output bus (I/O bus). The timing synchronization method includes the following steps. Multiple detection patterns are respectively and sequentially transmitted to the I/O bus through the chips. First, the detection patterns are sequentially transmitted through each of the at least one second chip. Then, the detection patterns are transmitted through the first chip. A synchronization pattern is transmitted to the I/O bus through the first chip. The synchronization pattern is monitored from the I/O bus through each of the at least one second chip. A given function is performed through each of the chips based on the synchronization pattern.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: executing a multi-stages programing on multiple physical units in a rewritable non-volatile memory module according to first data, where the multi-stages programing includes a first-stage programming and a second-stage programing; saving second data after the multi-stages programing is started and before the second-stage programing is completed, where the second data is generated by encoding the first data; and adjusting a read operation or a programming operation on at least one of the physical units according to the second data.

Abstract: A method for training an asymmetric generative adversarial network to generate an image and an electronic apparatus using the same are provided. The method includes the following. A first real image belonging to a first category, a second real image belonging to a second category and a third real image belonging to a third category are input to an asymmetric generative adversarial network for training the asymmetric generative adversarial network, and the asymmetric generative adversarial network includes a first generator, a second generator, a first discriminator and a second discriminator. A fourth real image belonging to the second category is input to the first generator in the trained asymmetric generative adversarial network to generate a defect image.

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method is described below. A read command sequence is transmitted, the read command sequence instructs to read a first physical unit, and the first physical unit belongs to a physical unit group. A first single-frame decoding is performed on a first data frame read from the first physical unit. First error evaluation information corresponding to the physical unit group is obtained in response to the first single-frame decoding being failed and a default condition not being satisfied. This default condition is used for triggering the multi-frame decoding on the physical unit group. A second single-frame decoding is performed on the first data frame according to the first error evaluation information.

Abstract: This disclosure proposes a data caching method and a host system. The host system includes a rewritable non-volatile memory module which includes multiple channels. The data caching method includes: obtaining a current token during an inference phase; reading a previous key matrix and a previous value matrix from the rewritable non-volatile memory module; generating a current key matrix according to the current token and the previous key matrix; generating a current value matrix according to the current token and the previous value matrix; writing multiple portions of the current key matrix into different channels; and writing multiple portions of the current value matrix into different channels.

Abstract: A fail recovery method, a memory storage device, and a memory control circuit unit are provided. The fail recovery method includes: in response to a first operation corresponding to a first physical unit failing, determining whether a current retry count is less than a predetermined count, in which the current retry count is used to represent a number of times an erase retry operation is performed on the first physical unit; in response to the current retry count being less than the predetermined count, performing the erase retry operation on the first physical unit; determining whether the erase retry operation is successful; and in response to the erase retry operation being successful, associating the first physical unit with a spare region.

Abstract: The disclosure provides a reading method, a memory storage device, and a memory control circuit unit. The reading method includes: applying a read pass voltage to memory cells of a first physical unit; calculating an open bit number of the memory cells connected to a bit line and cut off when the read pass voltage is applied for each bit line, wherein the open bit number corresponding to a first bit line is different from the open bit number corresponding to a second bit line; setting different read voltages; and applying a first read voltage to the memory cells connected to the first bit line in a second physical unit and applying a second read voltage to the memory cells connected to the second bit line in the second physical unit when reading the second physical unit, thereby obtaining data bits of the second physical unit.

Abstract: A decode control method, a memory storage device, and a memory control circuit unit are provided. The decode control method includes the following step. in response to a first decoding operation executed according to write data and first parity data failing, reading second parity data; executing a second decoding operation according to the second parity data; in response to the second decoding operation being successful, increasing a log likelihood ratio corresponding to the second parity data; and executing a third decoding operation according to the write data, the first parity data, and the second parity data.

Abstract: A memory control method, a memory storage device, and a memory control circuit unit for a rewritable non-volatile memory module are provided. The method includes: judging a load level of the rewritable non-volatile memory module; determining a suspend interval between a plurality of suspend commands according to the load level; and sequentially issuing the suspend commands to the rewritable non-volatile memory module according to the suspend interval. The suspend commands are configured to suspend an operation currently executed by the rewritable non-volatile memory module to execute a read operation. A time interval from an end of the read operation to receiving a next suspend command is greater than or equal to the suspend interval.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: setting a timer corresponding to a first physical unit after powering on; performing a read operation on the first physical unit and determining whether a data error condition is met; and marking the first physical unit as a bad physical unit when the data error condition is met and an elapsed time indicated by the timer is less than a threshold time.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: recording a random read count for each of multiple first physical units, in which each first physical unit stores valid data; initiating a data merging process; selecting multiple source physical units from the first physical units according to the random read count; and moving valid data in the source physical units to a target physical unit.

Abstract: A memory management method, including: acquiring multiple architecture parameters of an artificial intelligence model; obtaining a memory allocation size used in a training process of the artificial intelligence model according to the multiple architecture parameters; configuring a target memory region in random access memory according to the memory allocation size, wherein train processing stage in the training process of the artificial intelligence model shares the target memory region; and temporarily storing intermediate data corresponding to each train processing stage of the training process of the artificial intelligence model in the target memory region, wherein the intermediate data is transferred between accelerator processor module, the random access memory, and a storage device. Thereby, the present invention can automatically calculate the optimized memory allocation size, and through the design of shared memory space, effectively improve memory fragmentation issues.

Abstract: An encoding control method, a memory storage device, and a memory control circuit unit are provided. The encoding control method includes: obtaining write data; performing an encoding operation by an encoding circuit to generate first parity data and second parity data according to the write data, in which the second parity data is not generated according to the first parity data; sending a first write command sequence to instruct a storage of the write data, the first parity data, and the second parity data in a rewritable non-volatile memory module, in which the first parity data is used to perform a decoding operation with the write data, and the second parity data, along with the first parity data, is used to perform the decoding operation with the write data.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The memory management method includes: writing first data into N super physical programming units of a first super physical erasing unit in a plurality of super physical erasing units; generating N first temporary parity codes according to the first data and storing the N first temporary parity codes in a buffer memory; writing second data into M super physical programming units of a second super physical erasing unit in the plurality of super physical erasing units; performing an encoding operation on the second data and the N first temporary parity codes to generate N first parity codes; and writing the N first parity codes into the second super physical erasing unit.

Abstract: An error handling method, a memory storage device, and a memory control circuit unit are provided. The error handling method includes: calculating a first decoding rate of a first error handling process, where the first error handling process includes a plurality of decoding operations performed based on a first order; and in response to the first decoding rate being less than a first threshold, switching the first error handling process to a second error handling process, where the second error handling process includes a plurality of decoding operations performed based on a second order, where a decoding capability of a first decoding operation indicated by the second order is better than a decoding capability of a first decoding operation indicated by the first order.

Abstract: A memory management method is provided for a rewritable non-volatile memory module. The method includes: initiating a data merging operation; selecting a source physical unit and a target physical unit from the rewritable non-volatile memory module to perform the data merging operation; determining whether to create a backup table corresponding to a logical-to-physical mapping table; if it is determined to create the backup table, copying first data located at a first physical address in the source physical unit to a second physical address in the target physical unit, and recording the second physical address in the backup table; and determining whether to update the second physical address to the logical-to-physical mapping table based on information in the backup table.

Abstract: A training method for a machine learning model and a host system are provided. The host system includes a rewritable non-volatile memory module. The training method includes: executing a training process of the machine learning model, which includes, in an iteration at an epoch of the training process, storing transient data and backtracking data generated by the iteration in the rewritable non-volatile memory module; and in response to an abnormality occurring in the host system which causes an interruption in the iteration, reading the transient data and the backtracking data from the rewritable non-volatile memory module, determining a stage of the iteration based on the backtracking data, and resuming the stage according to the transient data.

Abstract: A data check method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. A connection between a memory storage device and a host system is established. First check data is generated according to first data. The first check data is maintained in the memory storage device. A cross-device write command is sent through the connection to store the first data into a memory in the host system. After the cross-device write command is sent, a cross-device read command is sent through the connection to read back the first data from the memory in the host system. In response to cross-device reading meeting a check trigger condition, a first check operation is performed on the read-back first data according to the check data to check whether the read back first data is abnormal. In response to the cross-device reading not meeting the check trigger condition, the first check operation is skipped.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a state of the memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein the operation mode includes a first operation mode and a second operation mode, and a first waiting time before the memory storage device entering a power saving mode in the first operation mode is longer than a second waiting time before the memory storage device entering the power saving mode in the second operation mode.