Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The memory management method includes: writing first data into N super physical programming units of a first super physical erasing unit in a plurality of super physical erasing units; generating N first temporary parity codes according to the first data and storing the N first temporary parity codes in a buffer memory; writing second data into M super physical programming units of a second super physical erasing unit in the plurality of super physical erasing units; performing an encoding operation on the second data and the N first temporary parity codes to generate N first parity codes; and writing the N first parity codes into the second super physical erasing unit.

Abstract: An error handling method, a memory storage device, and a memory control circuit unit are provided. The error handling method includes: calculating a first decoding rate of a first error handling process, where the first error handling process includes a plurality of decoding operations performed based on a first order; and in response to the first decoding rate being less than a first threshold, switching the first error handling process to a second error handling process, where the second error handling process includes a plurality of decoding operations performed based on a second order, where a decoding capability of a first decoding operation indicated by the second order is better than a decoding capability of a first decoding operation indicated by the first order.

Abstract: A memory management method is provided for a rewritable non-volatile memory module. The method includes: initiating a data merging operation; selecting a source physical unit and a target physical unit from the rewritable non-volatile memory module to perform the data merging operation; determining whether to create a backup table corresponding to a logical-to-physical mapping table; if it is determined to create the backup table, copying first data located at a first physical address in the source physical unit to a second physical address in the target physical unit, and recording the second physical address in the backup table; and determining whether to update the second physical address to the logical-to-physical mapping table based on information in the backup table.

Abstract: A training method for a machine learning model and a host system are provided. The host system includes a rewritable non-volatile memory module. The training method includes: executing a training process of the machine learning model, which includes, in an iteration at an epoch of the training process, storing transient data and backtracking data generated by the iteration in the rewritable non-volatile memory module; and in response to an abnormality occurring in the host system which causes an interruption in the iteration, reading the transient data and the backtracking data from the rewritable non-volatile memory module, determining a stage of the iteration based on the backtracking data, and resuming the stage according to the transient data.

Abstract: A data check method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. A connection between a memory storage device and a host system is established. First check data is generated according to first data. The first check data is maintained in the memory storage device. A cross-device write command is sent through the connection to store the first data into a memory in the host system. After the cross-device write command is sent, a cross-device read command is sent through the connection to read back the first data from the memory in the host system. In response to cross-device reading meeting a check trigger condition, a first check operation is performed on the read-back first data according to the check data to check whether the read back first data is abnormal. In response to the cross-device reading not meeting the check trigger condition, the first check operation is skipped.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a state of the memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein the operation mode includes a first operation mode and a second operation mode, and a first waiting time before the memory storage device entering a power saving mode in the first operation mode is longer than a second waiting time before the memory storage device entering the power saving mode in the second operation mode.

Abstract: A memory management method is provided for a rewritable non-volatile memory module. The method includes: initiating a data merging operation; selecting a source physical unit and a target physical unit from the rewritable non-volatile memory module to perform the data merging operation; determining whether to create a backup table corresponding to a logical-to-physical mapping table; if it is determined to create the backup table, copying first data located at a first physical address in the source physical unit to a second physical address in the target physical unit, and recording the second physical address in the backup table; and determining whether to update the second physical address to the logical-to-physical mapping table based on information in the backup table.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: detecting a first temperature status of a rewritable non-volatile memory module; performing a first write operation on a first physical unit under the first temperature status to store first data to the first physical unit; after performing the first write operation, detecting a second temperature status of the rewritable non-volatile memory module; in response to the first temperature status and the second temperature status meeting a first condition, performing a data refresh operation on the first physical unit under the second temperature status to re-store the first data to a second physical unit different from the first physical unit.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: setting an initial value of count information corresponding to at least one of a plurality of physical management units to be greater than zero; setting initial values of count information corresponding to at least two of the physical management units to be different from each other; and updating first count information corresponding to a first physical management unit among the physical management units according to a first operation performed on the first physical management unit, wherein the first count information reflects a reference number of times of performing the first operation on the first physical management unit, and the reference number of times is greater than an actual number of times of performing the first operation on the first physical management unit.

Abstract: A memory control method, a memory storage device, and a memory control circuit unit for a rewritable non-volatile memory module are provided. The method includes: judging a load level of the rewritable non-volatile memory module; determining a suspend interval between a plurality of suspend commands according to the load level; and sequentially issuing the suspend commands to the rewritable non-volatile memory module according to the suspend interval. The suspend commands are configured to suspend an operation currently executed by the rewritable non-volatile memory module to execute a read operation. A time interval from an end of the read operation to receiving a next suspend command is greater than or equal to the suspend interval.

Abstract: A wear leveling method, a memory storage device and a memory control circuit unit are provided. The wear leveling method includes: obtaining an open bit count of each physical erasing unit; determining whether there is a first physical erasing unit with the open bit count greater than a first threshold; and in response to there being the first physical erasing unit with the open bit count greater than the first threshold, performing a first wear leveling operation on the first physical erasing unit.

Abstract: A signal receiving circuit, a memory storage device, and a reference voltage adjustment method are provided. The method includes: obtaining a first signal and a plurality of reference voltage levels; sensing a voltage relative relationship between the first signal and the plurality of reference voltage levels, where the voltage relative relationship reflects bit data carried by the first signal; detecting edge information of the first signal; and adjusting at least one of the plurality of reference voltage levels according to the edge information.

Abstract: A clock signal control method is provided according to an exemplary embodiment of the disclosure. In the method, an access operation is executed on a volatile memory module through a memory interface circuit, and a duty cycle of a first clock signal is set according to a type of the access operation. Furthermore, the first clock signal is transmitted to the volatile memory module to execute the access operation.

Abstract: An electrical parameter adjustment method, a memory storage device, and a memory control circuit unit are provided. The method includes: detecting a status of a rewritable non-volatile memory module; in response to the status of the rewritable non-volatile memory module meeting a first condition, sending a single-state read command, wherein the single-state read command instructs reading a first physical unit based on a specific voltage, and the specific voltage is a read pass voltage corresponding to the first physical unit; and adjusting at least one electrical parameter of the rewritable non-volatile memory according to a read result of the single-state read command.

Abstract: A data check method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. A connection between a memory storage device and a host system is established. First check data is generated according to first data. The first check data is maintained in the memory storage device. A cross-device write command is sent through the connection to store the first data into a memory in the host system. After the cross-device write command is sent, a cross-device read command is sent through the connection to read back the first data from the memory in the host system. In response to cross-device reading meeting a check trigger condition, a first check operation is performed on the read-back first data 10 according to the check data to check whether the read back first data is abnormal. In response to the cross-device reading not meeting the check trigger condition, the first check operation is skipped.

Abstract: A spread spectrum clock generator, a memory storage device, and a spread spectrum clock generation method are provided. The method includes: generating a spread spectrum clock signal according to a reference clock signal and a control signal; and adjusting the control signal to change a frequency of the spread spectrum clock signal based on multiple frequency change rates, wherein an initial frequency change rate of the spread spectrum clock is greater than a frequency change rate of the spread spectrum clock within a target time range.

Abstract: A multi-layer circuit board structure and a memory storage device are disclosed. The multi-layer circuit board structure includes a first capacity component, a second capacity component, a first conductor, and a first via hole. The first via hole is connected to the first conductor. At a first layer of the multi-layer circuit board structure, a first capacity component and a second capacity component are arranged oppositely. The first capacity component is connected to a first extension part of the first conductor. The second capacity component is connected to a second extension part of the first conductor. The first via hole is connected to a third extension part of the first conductor, and the first via hole is disposed between the first capacity component and the second capacity component.

Abstract: A decoding method, comprising: sending a first read command sequence corresponding to a host system to read a first physical unit of a physical unit group to obtain a first data frame; responding to a decoding failure of a first single-frame decoding performed on the first data frame, sending a plurality of second read command sequences to read a plurality of second physical units in the physical unit group to obtain a plurality of second data frames; respectively performing a second single-frame decoding on the second data frames; performing a XOR operation on the corresponding data frame of each physical unit of the physical unit group to obtain first error evaluation information; generating enhanced first error evaluation information based on the first error evaluation information; and performing a third single-frame decoding on the first data frame based on the enhanced first error evaluation information.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The memory management method includes: writing first data into N super physical programming units of a first super physical erasing unit in a plurality of super physical erasing units; generating N first temporary parity codes according to the first data and storing the N first temporary parity codes in a buffer memory; writing second data into M super physical programming units of a second super physical erasing unit in the plurality of super physical erasing units; performing an encoding operation on the second data and the N first temporary parity codes to generate N first parity codes; and writing the N first parity codes into the second super physical erasing unit.