Patents Assigned to Phison Electronics Corp.
  • Publication number: 20220365706
    Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.
    Type: Application
    Filed: June 2, 2021
    Publication date: November 17, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Wei Lin, Shih-Jia Zeng, An-Cheng Liu, Yu-Cheng Hsu
  • Publication number: 20220342547
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 27, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Yu-Cheng Hsu, Tsai-Hao Kuo, Wei Lin, An-Cheng Liu
  • Publication number: 20220342765
    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes the following. When the memory storage device is powered-on, it is determined whether a power loss state of the memory storage device matches an unexpected power loss state according to a power-off instruction. Data is written into a plurality of physical programming units using a single-page programming mode and not using a multi-page programming mode when it is determined that the power loss state matches the unexpected power loss state.
    Type: Application
    Filed: June 3, 2021
    Publication date: October 27, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Publication number: 20220334723
    Abstract: A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 20, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Wei Lin, An-Cheng Liu, Yu-Heng Liu, Chun-Hsi Lai, Ting-Chien Zhan
  • Publication number: 20220334920
    Abstract: A method for managing a host memory buffer, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting whether a system abnormality occurs; copying a first command and first data corresponding to the first command stored in a data buffer of a host system to the memory storage apparatus in response to determining that the system abnormality occurs; executing an initial operation after copying the first command and the first data, wherein the initial operation initializes a part of a hardware circuit in the memory storage apparatus and does not initialize another part of the hardware circuit in the memory storage apparatus; and re-executing the first command stored in the memory storage apparatus after initializing the part of the hardware circuit.
    Type: Application
    Filed: May 3, 2021
    Publication date: October 20, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hsiao-Chi Ho
  • Patent number: 11467773
    Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 11, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Yu-Chung Shen, Nien-Hung Lin
  • Patent number: 11467758
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: October 11, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chieh Yang, Yi-Hsuan Lin, Tai-Yuan Huang, Ping-Chuan Lin
  • Patent number: 11455243
    Abstract: A data merge method for a rewritable non-volatile memory module including multiple physical units is provided. The method includes: starting a first data merge operation, and selecting at least one first physical unit for executing the first data merge operation and at least one second physical unit for executing a second data merge operation from the physical units; reading first mapping information from the rewritable non-volatile memory module, and copying first valid data collected from the at least one first physical unit to at least one third physical unit in the physical units; identifying second valid data in the at least one second physical unit according to the first mapping information in the first data merge operation; and starting the second data merge operation, and copying the second valid data collected from the at least one second physical unit to at least one fourth physical unit in the physical units.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: September 27, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20220293185
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 15, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Wei Lin, An-Cheng Liu, Yu-Heng Liu, Chun-Hsi Lai, Ting-Chien Zhan
  • Patent number: 11442662
    Abstract: A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a write command from a host system; and determining whether to write a data corresponding to the write command into a first area or a second area according to a write amplification factor of the first area, where if it is determined to write the data into the second area, copying the written data to the first area after writing the data.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 13, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Hsiang-Jui Huang, Ping-Yu Hsieh, Tsung-Ju Wu
  • Publication number: 20220283740
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes receiving first data from a host system; sending a first write command sequence instructing continuous writing of the first data to a plurality of first chip enabled (CE) regions in response to the memory storage device being in a first state; receiving second data from the host system; and sending a second write command sequence instructing continuous writing of the second data to at least one second CE region in response to the memory storage device being in a second state. A data amount of the first data is equal to a data amount of the second data. A total number of the first CE regions is greater than a total number of the at least one second CE region.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 8, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11430538
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: August 30, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Pochiao Chou, Cheng-Che Yang
  • Publication number: 20220269581
    Abstract: A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.
    Type: Application
    Filed: March 15, 2021
    Publication date: August 25, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chien Chang Tseng
  • Publication number: 20220254431
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.
    Type: Application
    Filed: March 8, 2021
    Publication date: August 11, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Pochiao Chou, Cheng-Che Yang
  • Patent number: 11409472
    Abstract: A trim command processing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a trim command from a host system, where the trim command is configured to indicate data stored in at least one logical address among a plurality of logical addresses can be erased; calculating a first data volume of data required to be programmed when a data trim operation is performed according to the trim command; and determining whether to perform a first trim operation or a second trim operation according to the first data volume.
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: August 9, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11409596
    Abstract: An encoding control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first data units by a plurality of first host to device (H2D) access operations; generating at least one first parity unit according to the first data units; transmitting the first parity unit to the host system by at least one first device to host (D2H) access operation; reading a plurality of second data units by a plurality of second H2D access operations; generating at least one second parity unit according to the first parity unit and the second data units without reading the first parity unit from the host system; transmitting the second parity unit to the host system by at least one second D2H access operation; and storing the first data units and the second data units to a first physical unit.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: August 9, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20220245024
    Abstract: An encoding control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first data units by a plurality of first host to device (H2D) access operations; generating at least one first parity unit according to the first data units; transmitting the first parity unit to the host system by at least one first device to host (D2H) access operation; reading a plurality of second data units by a plurality of second H2D access operations; generating at least one second parity unit according to the first parity unit and the second data units without reading the first parity unit from the host system; transmitting the second parity unit to the host system by at least one second D2H access operation; and storing the first data units and the second data units to a first physical unit.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 4, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20220229592
    Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.
    Type: Application
    Filed: February 17, 2021
    Publication date: July 21, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Yu-Chung Shen, Nien-Hung Lin
  • Patent number: 11392164
    Abstract: A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 19, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Sheng-Wen Chen, Shih-Yang Sun, Zhen-Hong Hung
  • Patent number: 11372590
    Abstract: A memory control method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit in response to a first read command from a host system; performing a first decoding operation on the first data to obtain decoded data corresponding to the first data; storing the decoded data corresponding to the first data in a buffer memory; reading second data from the first physical unit in response to a second read command from the host system; performing a second decoding operation on the second data; and in response to failure of the second decoding operation, searching the buffer memory for the decoded data corresponding to the first data to replace the reading of the second data.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: June 28, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chia-Hsiung Lai