Patents Assigned to Phison Electronics Corp.
  • Publication number: 20240201857
    Abstract: A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.
    Type: Application
    Filed: February 14, 2023
    Publication date: June 20, 2024
    Applicant: Phison Electronics Corp.
    Inventors: Po-Cheng Su, Yu-Cheng Hsu, Wei Lin
  • Publication number: 20240192868
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: in a first operation mode, setting a physical management unit to cross N physical regions in a rewritable non-volatile memory module; in a second operation mode, setting the physical management unit to cross M physical regions in the rewritable non-volatile memory module, wherein N is greater than M; and accessing the rewritable non-volatile memory module based on the physical management unit.
    Type: Application
    Filed: February 1, 2023
    Publication date: June 13, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 12008242
    Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: June 11, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yi-Chung Chen, Ming-Chien Huang
  • Patent number: 12008239
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: June 11, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Patent number: 12008262
    Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 11, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Chih-Wei Wang, Wei Lin
  • Publication number: 20240184449
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.
    Type: Application
    Filed: January 9, 2023
    Publication date: June 6, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Publication number: 20240168641
    Abstract: A data storage method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving at least one write command instructing to store target data from a host system; encoding the target data to generate parity data; and respectively storing the target data and the parity data in a first physical management unit and a second physical management unit, and each of the first physical management unit and the second physical management unit crosses multiple chip enabled (CE) regions. In addition, in the first physical management unit, first data is stored in a first chip enabled region among the chip enabled regions. In the second physical management unit, first parity data for protecting the first data is stored in a second chip enabled region among the chip enabled regions, and the first chip enabled region is different from the second chip enabled region.
    Type: Application
    Filed: December 25, 2022
    Publication date: May 23, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11983069
    Abstract: A data rebuilding method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: establishing a connection between the memory storage apparatus and a host system; storing a first data to a memory of the host system via the connection; detecting an error in the first data in the memory; and rebuilding a part of data in the first data in the memory according to the error.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: May 14, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Horng-Sheng Yan
  • Publication number: 20240152296
    Abstract: A data reading method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving a read command from a host system, and the read command instructs reading data from at least one logical unit, and the logical unit is mapped to a first physical unit; obtaining state information of at least two neighboring memory cells in the first physical unit; determining an electrical parameter offset value corresponding to the neighboring memory cells according to the state information; and sending a read command sequence according to the electrical parameter offset value, and the read command sequence instructs reading the first physical unit based on at least one electrical parameter, and the electrical parameter is controlled by the electrical parameter offset value.
    Type: Application
    Filed: December 7, 2022
    Publication date: May 9, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Heng Liu, Yu-Siang Yang, An-Cheng Liu, Wei Lin
  • Patent number: 11977745
    Abstract: A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: May 7, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Chia-Lung Ma, Zhen-Yu Weng
  • Publication number: 20240143182
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving multiple read commands at least instructing to read first data stored in a first plane and second data stored in a second plane from a host system; sending multiple read command sequences at least instructing to execute a first read operation on the first plane to obtain the first data and to execute a second read operation on the second plane to obtain the second data according to the read commands; determining a data transmission order according to performance of the first read operation and the second read operation; and sequentially receiving the first data and the second data from a rewritable non-volatile memory module according to the data transmission order.
    Type: Application
    Filed: November 25, 2022
    Publication date: May 2, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Hsiang Lee
  • Publication number: 20240143190
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving first data from a host system; encoding the first data to generate first parity data based on a first code rate; storing the first data and the first parity data in a plurality of first physical management units; collecting second data from a rewritable non-volatile memory module; encoding the second data to generate second parity data based on a second code rate, wherein the first code rate is different from the second code rate; and storing the second data and the second parity data in a plurality of second physical management units.
    Type: Application
    Filed: December 2, 2022
    Publication date: May 2, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20240145952
    Abstract: A gold finger connector and a memory storage device are disclosed. The gold finger connector includes: a connector body, a pin carrier, a plurality of first pins, a plurality of second pins, and at least one signal shielding structure. The pin carrier is protruded out of the connector body. The first pins are disposed on a first surface of the pin carrier. The second pins are disposed on the first surface and at least partially staggered with the first pins. The at least one signal shielding structure is disposed on the pin carrier and configured to conduct at least one target pin in the second pins to at least one ground layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: May 2, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Zong-Sian Ye, Yang-Tse Hung, Jin-Jia Chang, Bo-Yuan Wu
  • Patent number: 11972139
    Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 30, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Hsiao-Yi Lin, Wei Lin
  • Publication number: 20240128987
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
    Type: Application
    Filed: November 28, 2022
    Publication date: April 18, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
  • Publication number: 20240126313
    Abstract: A regulator circuit module, a memory storage device, and a voltage control method are disclosed. The method includes: generating an output voltage according to an input voltage by a driving circuit; generating a feedback voltage according to the output voltage; controlling the driving circuit to adjust the output voltage according to the feedback voltage by a regulator circuit; compensating an output of the regulator circuit by a compensating circuit; and activating or deactivating the compensating circuit according to an input bypass-voltage of a switch circuit.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 18, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Po-Chih Ku
  • Patent number: 11960381
    Abstract: A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chien Chang Tseng
  • Patent number: 11962328
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
  • Patent number: 11960762
    Abstract: A method for managing a memory buffer, a memory control circuit unit, and a memory storage apparatus are provided. The method includes the following steps. Multiple consecutive first commands are received from a host system. A command ratio of read command among the first commands is calculated. The memory storage apparatus is being configured in a first mode or a second mode according to the command ratio and a ratio threshold. A first buffer is configured in a buffer memory to temporarily store a logical-to-physical address mapping table in response to the memory storage device being configured in the first mode, in which the first buffer has a first capacity. A second buffer is configured in the buffer memory in response to the memory storage device being configured in the second mode, in which the second buffer has a second capacity, which is greater than the first capacity.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Po-Wen Hsiao, Chun Hao Lin
  • Patent number: 11960761
    Abstract: A memory control method is disclosed according to an embodiment. The method includes: temporarily storing first type data into a buffer memory, wherein the first type data is preset to be stored into a rewritable non-volatile memory module based on a first programming mode; in a state that the first type data is stored in the buffer memory, temporarily storing second type data into the buffer memory, and the second type data is preset to be stored into the rewritable non-volatile memory module based on a second programming mode different from the first programming mode; and in a state that a data volume of the first type data in the buffer memory does not reach a first threshold, if a data volume of the second type data in the buffer memory reaches a second threshold, storing the first type data in the buffer memory into the rewritable non-volatile memory module.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chun-Yang Hu, Yi-Tein Hung