Patents Assigned to Phison Electronics Corp.
  • Publication number: 20230289102
    Abstract: An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.
    Type: Application
    Filed: April 20, 2022
    Publication date: September 14, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Bo Lun Huang
  • Patent number: 11755242
    Abstract: A data merging method can copy a new logical to physical mapping table and update a copied logical to physical mapping table according to a physical address of a recycling unit expected to be written at the same time. In this way, the number of times that the same logic to physical mapping table is read multiple times during the data merging operation can be reduced to improve the execution efficiency of the data merging operation, thereby increasing the system performance of the memory storage device.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: September 12, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Li Hsun Lien
  • Patent number: 11757684
    Abstract: A retiming circuit module, a signal transmission system, and a signal transmission method are provided. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes built-in first signal transmission path and second signal transmission path. The multipath signal transmission circuit may perform first signal transmission between an upstream device and a downstream device based on a first signal transmission frequency and the second signal transmission path. During a period of performing the first signal transmission, the path control circuit may detect a first data sequence transmitted between the upstream device and the downstream device.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: September 12, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chun-Wei Chang, Ching-Jui Hsiao, Jen-Chu Wu, Yuwei Kuo
  • Publication number: 20230283065
    Abstract: An over-voltage protection device, a memory storage device, and an over-voltage protection method are provided. The over-voltage protection device includes a main load switch, multiple power channels, a voltage detection circuit, and a control circuit. The main load switch is configured to receive power and provide the power to a first power channel among the power channels. The voltage detection circuit is configured to detect a power abnormal status of a second power channel among the power channels. The control circuit is configured to control the main load switch to stop power supply to the first power channel according to the power abnormal status.
    Type: Application
    Filed: March 30, 2022
    Publication date: September 7, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Shu-Han Chou
  • Publication number: 20230281114
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: generating a first operation command via one of a plurality of processing circuits, wherein the first operation command instructs to access a first memory group in a plurality of memory groups; and in response to a first state information, sending a first command sequence to the first memory group according to the first operation command to instruct the first memory group to perform an access operation. The first state information reflects a first activation state of the plurality of memory groups, and the first command sequence does not include a control command sequence configured to activate the first memory group.
    Type: Application
    Filed: April 21, 2022
    Publication date: September 7, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Sheng-Min Huang, Shih-Ying Song
  • Publication number: 20230259306
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: performing a first write operation based on a first programming mode to sequentially write first data to a plurality of first chip enabled regions via a plurality of channels; after the first write operation is performed, performing a second write operation based on a second programming mode to sequentially write second data to the first chip enabled regions and at least one second chip enabled region via the channels. A total number of the first chip enabled regions is larger than a total number of the second chip enabled region.
    Type: Application
    Filed: March 14, 2022
    Publication date: August 17, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Teng-Chun Hsu, Chang Han Hsieh
  • Patent number: 11726709
    Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 15, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yu-Siang Yang, Szu-Wei Chen, Wei Lin
  • Publication number: 20230221863
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.
    Type: Application
    Filed: February 15, 2022
    Publication date: July 13, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Sheng-Min Huang, Kuo-Hwa Ho, Shih-Ying Song
  • Publication number: 20230221884
    Abstract: A command management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: obtaining a plurality of commands from a memory of a host system; storing the commands in a first buffer region of the memory storage device; in response to a first command and a second command meeting a pairing condition in the first buffer region, putting the first command and the second command in the first buffer region in a first command queue of the memory storage device; and continuously executing the first command and the second command in the first command queue.
    Type: Application
    Filed: February 16, 2022
    Publication date: July 13, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Ming-Hui Tseng
  • Publication number: 20230214150
    Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 6, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Hsiao-Yi Lin, Wei Lin
  • Patent number: 11687444
    Abstract: A data managing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: receiving a write command for writing a plurality of first data into a rewritable non-volatile memory module; when the plurality of first data are continuous data, writing the plurality of first data respectively into a plurality of first physical erasing units by using a single-page programming mode, and recording first management information corresponding to the plurality of first physical erasing units; and when the plurality of first data are not the continuous data, writing the plurality of first data respectively into a plurality of second physical erasing units by using the single-page programming mode.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: June 27, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20230195361
    Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.
    Type: Application
    Filed: January 17, 2022
    Publication date: June 22, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Po-Cheng Su, Chih-Wei Wang, Wei Lin
  • Publication number: 20230176783
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.
    Type: Application
    Filed: January 22, 2022
    Publication date: June 8, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Po-Cheng Su, Chih-Wei Wang, Yu-Cheng Hsu, Wei Lin
  • Patent number: 11669394
    Abstract: A crossing frames encoding management method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: reading a tag swap information corresponding to a first physical group; encoding a first data; storing a first part of the encoded first data to at least one first physical unit corresponding to a first tag information in the first physical group; and storing a second part of the encoded first data to at least one second physical unit corresponding to a second tag information in the first physical group according to the tag swap information. The first tag information corresponds to a first crossing frames encoding group. The second tag information corresponds to a second crossing frames encoding group. The first crossing frames encoding group is different from the second crossing frames encoding group.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: June 6, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Kuang-Yao Chang, Cheng-Jui Chang
  • Publication number: 20230141062
    Abstract: A switching power supply module and a memory storage device are disclosed. The switching power supply module includes a first voltage regulation circuit, a second voltage regulation circuit, a switch circuit and a control circuit. The first voltage regulation circuit is configured to regulate an original power as a first power. The second voltage regulation circuit is configured to regulate the original power as a second power. The control circuit is configured to control the switch circuit to conduct a first power supply path under a first status to provide the first power to the first power supply target. The control circuit is further configured to control the switch circuit to conduct a second power supply path under a second status to provide the second power to the second power supply target.
    Type: Application
    Filed: December 3, 2021
    Publication date: May 11, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Shu-Han Chou
  • Publication number: 20230127395
    Abstract: An overcurrent protection circuit, a memory storage device, and an overcurrent protection method are disclosed. The overcurrent protection circuit includes a load switch, a first mirror circuit, a second mirror circuit, and a control circuit. The first mirror circuit is configured to generate a first node voltage in a state that a voltage difference between two terminals of the load switch is within a first voltage region. The second mirror circuit is configured to generate a second node voltage in a state that the voltage difference between the two terminals of the load switch is within a second voltage region. The control circuit is configured to cut off the load switch according to at least one of the first node voltage and the second node voltage to perform an overcurrent protection. The first voltage region is different from the second voltage region.
    Type: Application
    Filed: December 8, 2021
    Publication date: April 27, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Shu-Han Chou
  • Patent number: 11635777
    Abstract: A temperature control circuit for an electronic device is provided. The temperature control circuit includes a temperature detector, a status detection circuit and a control circuit. The temperature detector is configured to detect a temperature of the electronic device and generate first evaluation information. The status detection circuit is configured to detect a work status of at least one circuit module in the electronic device and generate second evaluation information. The control circuit is configured to adjust at least one electronic parameter of the electronic device according to the first evaluation parameter and the second evaluation parameter to control the temperature of the electronic device.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: April 25, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Jia-Huei Yeh, Chao-Ta Huang, Yi-Feng Li, Po-Chieh Chiu, Chun-Yu Ling
  • Patent number: 11636902
    Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: April 25, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Guan-Wei Wu, Jen-Chu Wu, Jen-Huo Wang, Yu-Chiang Liao, Shih-Yang Sun
  • Patent number: 11615848
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: March 28, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Wei Lin, An-Cheng Liu, Yu-Heng Liu, Chun-Hsi Lai, Ting-Chien Zhan
  • Patent number: 11614997
    Abstract: A method for managing a host memory buffer, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting whether a system abnormality occurs; copying a first command and first data corresponding to the first command stored in a data buffer of a host system to the memory storage apparatus in response to determining that the system abnormality occurs; executing an initial operation after copying the first command and the first data, wherein the initial operation initializes a part of a hardware circuit in the memory storage apparatus and does not initialize another part of the hardware circuit in the memory storage apparatus; and re-executing the first command stored in the memory storage apparatus after initializing the part of the hardware circuit.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 28, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hsiao-Chi Ho