Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

Abstract: A signal transmission circuit of an electronic device is provided. The electronic device is coupled to a signal reception circuit of a host via the signal transmission circuit. The signal transmission circuit includes a driving circuit module and a signal detection module. The driving circuit module provides at least one initialized signal and a detection signal. The initialized signal is output prior to the detection signal. The signal detection module is coupled to the signal reception circuit via a signal detection terminal. The initialized signal reduces a signal reference level of a reception terminal of the signal reception circuit. The signal detection module determines the type of the transmission interface of the signal reception circuit according to whether the detection signal of the signal detection terminal satisfies a predetermined threshold value. Furthermore, a method for detecting the signal transmission interface is provided.

Abstract: A memory storage apparatus having a rewritable non-volatile memory module, a first circuit, a memory controller and a power management circuit is provided. The first circuit outputs a state signal and keeps the state signal in a first state when the first circuit is enabled, and then the first circuit keeps the state signal in a second state after a predetermined condition is satisfied. When the memory controller receives a first signal, the power management circuit stops supplying an output voltage to the rewritable non-volatile memory module and the memory controller. Additionally, when the memory controller is enabled, the memory controller determines whether the state signal is in the first state. If true, the memory controller performs a first procedure; and if not, the memory controller performs a second procedure.

Abstract: A data writing method for writing data into a physical block of a rewritable non-volatile memory module is provided. The method includes setting danger distance respectively corresponding to each of the physical pages of the physical block, and setting a secure writing flag in an enable state in response to a secure write command. The method also includes determining whether the secure writing flag is set in the enable state when receiving a write command and updated data thereof; if no, writing the updated data into a predetermined physical page of the physical block; if yes, writing the updated data into a secure physical page of the physical block and re-setting the secure writing flag in a disable state, and the distance between the secure physical page and the predetermined physical page is equal to the danger distance corresponding to the predetermined physical page.

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes determining a corresponding read voltage based on a critical voltage distribution of memory cells of a word line. The method further includes: if the critical voltage distribution of the memory cells is a right-offset distribution, applying a set of right adjustment read voltage to the word line to read a plurality of bit data as corresponding soft values; and decoding the corresponding soft values to obtain page data stored in the memory cells. Herein, the set of right adjustment read voltage includes a plurality of positive adjustment read voltages and a plurality of negative adjustment read voltages and the number of the positive adjustment read voltages is more than the number of the negative adjustment read voltages. Accordingly, storage states of the memory cells can be identified correctly.

Abstract: A data reading method adapted to a rewritable non-volatility memory module having physical blocks is provided, wherein each physical block has a plurality of physical pages. In the data reading method, each physical page is partitioned into bit data areas, where at least one of the bit data areas has a data length different from that of the other bit data areas. Data is written into the bit data areas. Data in each bit data area is corresponding to an ECC frame. The data is read from the bit data areas. Because the at least one of bit data areas has a relatively short data length, the error correction capability is improved and the data can be correctly read. An error bit information is obtained according to the read data. A log likelihood ratio (LLR) lookup table or a threshold voltage is adjusted according to the error bit information.

Abstract: A key transport method for transporting a key from a buffer memory to an encryption/decryption unit is provided. The method includes logically dividing bits of the key into key segments, wherein each of the key segments has a start position and a segment length. The method also includes setting a transmission length belonging to each of key segments based on the start positions and the segment lengths of the key segments; assigning a transmission bit stream belonging to each of the key segments from the bits of the key according to the start positions and the transmission lengths of the key segments; determining a transmission sequence; and sending the start position, the segment length and the transmission bit stream belonging to each of the key segments to the encryption/decryption unit from the buffer memory based on the transmission sequence. Accordingly, the method can transport the key safely.

Abstract: A method of storing system data, and a memory controller and a memory storage apparatus using the same are provided. The method includes determining whether the unused storage space of a system physical erase unit is enough for storing updated system data. The method further includes, if the unused storage space of the system physical erase unit is not enough for storing the updated system data, selecting an empty physical erase unit, writing the updated system data into at least one first physical program unit of the selected physical erase unit and writing dummy data into a second physical program unit of the selected physical erase unit.

Abstract: A method and a system for protecting data, a storage device, and a storage device controller are provided. In the present method, when a host accesses data in the storage device, whether the host performs a play operation or a copy operation on the data is first determined. If the host performs the play operation on the data, the storage device continues to execute the play operation so as to allow the host to access the data. On the other hand, if the host performs the copy operation on the data, the storage device executes an interference procedure so as to prevent or retard the data from being copied into the host.

Abstract: A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.

Abstract: A data writing method for a rewritable non-volatile memory module containing physical blocks is provided. The method includes: configuring virtual block address to map to at least a part of the logical blocks; receiving a write command which instructs to write file data to the first virtual block addresses, and the first virtual block addresses are mapped to first logical blocks of the at least the part of the logical blocks. The method further includes: writing the file data into the physical blocks mapped to a plurality of second logical blocks; determining whether a program failure is occurred during the writing period; and if the program failure is not occurred, the first virtual block addresses are remapped to the second logical block. Accordingly, the method can ensure the update completeness of the file data.

Abstract: A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.

Abstract: A command executing method for a memory storage apparatus and a memory controller and the memory storage apparatus using the same are provided. The method includes, during a data merging operation, receiving a write command and a write data corresponding to the write command from a host system. The method also includes temporarily storing the write data into a buffer memory, and at a delay time point, transmitting a response message to the host, the delay time point is set by adding a dummy delay time to a time point that the operation of writing the write data into the buffer memory is completed. Accordingly, the method can effectively level the response times of executing write commands during the data merging operation, thereby shortening the maximum access time.

Abstract: A data merging method for merging data belonging to a first logical block in a rewritable non-volatile memory module is provided. The method includes getting a second physical block from a free area of the rewritable non-volatile memory module and determining whether a valid logical page number is smaller than a predetermined number. The method also includes, when the valid logical page number is smaller than the predetermined number, storing a corresponding page mapping table in a start physical page of the second physical block and writing at least one valid page data belonging to the first logical block into at least one physical page of the second physical block. Accordingly, the method can effectively shorten the time for merging data.

Abstract: A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip has a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks of the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip.

Abstract: A signal processing method, a connector and a memory storage device are provided. The signal processing method is for the connector which does not include a crystal oscillator. The signal processing method includes: receiving a first signal stream from a host system; tracking a transmission frequency of the first signal stream, and obtaining a frequency shift quantity of the first signal stream relative to the transmission frequency; determining if a spread spectrum operation is performed on the first signal stream according to the frequency shift quantity to generate a determination result; generating a second signal stream according to the determination result and the transmission frequency. Accordingly, the spread spectrum operation is handled under the situation without a crystal oscillator.

Abstract: A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.

Abstract: A voltage controlled oscillator module including a VCO unit and a gain adjustment unit is provided. The VCO unit is configured to generate a frequency signal based on a control voltage. The gain adjustment unit is coupled to the VCO unit and configured to receive a first adjustment voltage, a second adjustment voltage, and a reference voltage and accordingly adjusts the control voltage to adjust a frequency value of the frequency signal. The gain adjustment unit includes an adjustment circuit unit and a reference circuit unit. A first voltage-frequency curve of the frequency value of the frequency signal and a voltage value of the first adjustment voltage changes in response to a structure characteristic of the adjustment circuit unit. Furthermore, a frequency generating system and a method for adjusting a signal frequency of the VCO module are provided.

Abstract: A controller capable of preventing spread of computer viruses is provided. The controller includes a microprocessor unit, and a first interface unit, a second interface unit, a comparing unit and a filter unit which are coupled to the microprocessor unit. The first interface unit is coupled to a storage medium, and the second interface unit is coupled to a computer host. The comparing unit determines whether data read form the storage medium by the computer host is an automatic executing file. And, the filter unit replaces the read data with a predetermined data and transmit the predetermined data to the computer host when the read data is the automatic executing file. Accordingly, the controller is capable of preventing the spread of the computer viruses designed in an automatic executing file.

Abstract: A data protection method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. The data protection method includes following steps. If the rewritable non-volatile memory module is powered on, a power-off period from last time the rewritable non-volatile memory module is powered off till present is obtained. If the power-off period is longer than a time threshold, whether each physical block satisfies an update condition is determined according to a block information of the physical block. An update procedure is executed on the physical blocks that satisfy the update condition. The update procedure is configured to read data from a physical block and rewrite the data into one of the physical blocks. Thereby, data in the physical blocks is protected from being easily lost, and the lifespan of the rewritable non-volatile memory module is prolonged.