Patents Assigned to Phison Electronics Corp.
  • Patent number: 11609822
    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes the following. When the memory storage device is powered-on, it is determined whether a power loss state of the memory storage device matches an unexpected power loss state according to a power-off instruction. Data is written into a plurality of physical programming units using a single-page programming mode and not using a multi-page programming mode when it is determined that the power loss state matches the unexpected power loss state.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 21, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11604586
    Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: March 14, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Hsiao-Yi Lin, Yu-Siang Yang
  • Publication number: 20230071724
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: detecting a first temperature status of a rewritable non-volatile memory module; performing a first write operation on a first physical unit under the first temperature status to store first data to the first physical unit; after performing the first write operation, detecting a second temperature status of the rewritable non-volatile memory module; in response to the first temperature status and the second temperature status meeting a first condition, performing a data refresh operation on the first physical unit under the second temperature status to re-store the first data to a second physical unit different from the first physical unit.
    Type: Application
    Filed: October 12, 2021
    Publication date: March 9, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Jia-Fan Chien, Wei Lin, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 11599457
    Abstract: A decoding circuit module, a memory control circuit unit, and a memory storage device are disclosed. The decoding circuit module is configured to decode data read from a rewritable non-volatile memory module and the decoding circuit module includes a first buffer, a second buffer, a first decoding circuit, and a second decoding circuit. The first decoding circuit is configured to decode first data read from the rewritable non-volatile memory module and stored in the first buffer. The second decoding circuit is configured to decode second data read from the rewritable non-volatile memory module and stored in the second buffer. A data decoding ability of the first decoding circuit is different from a data decoding ability of the second decoding circuit. The second data is stored in the second buffer via the first buffer and is not decoded by the first decoding circuit.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: March 7, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Sheng-Min Huang
  • Publication number: 20230048903
    Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
    Type: Application
    Filed: September 8, 2021
    Publication date: February 16, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Guan-Wei Wu, Jen-Chu Wu, Jen-Huo Wang, Yu-Chiang Liao, Shih-Yang Sun
  • Publication number: 20230037782
    Abstract: A method for training an asymmetric generative adversarial network to generate an image and an electronic apparatus using the same are provided. The method includes the following. A first real image belonging to a first category, a second real image belonging to a second category and a third real image belonging to a third category are input to an asymmetric generative adversarial network for training the asymmetric generative adversarial network, and the asymmetric generative adversarial network includes a first generator, a second generator, a first discriminator and a second discriminator. A fourth real image belonging to the second category is input to the first generator in the trained asymmetric generative adversarial network to generate a defect image.
    Type: Application
    Filed: August 29, 2021
    Publication date: February 9, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yi-Hsiang MA, Szu-Wei Chen, Yu-Hung Lin, An-Cheng Liu
  • Patent number: 11573704
    Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: February 7, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Hsiao-Yi Lin, Yu-Siang Yang
  • Patent number: 11575496
    Abstract: A retiming circuit module, a signal transmission system and a signal transmission method are disclosed. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes a plurality of parallel signal transmission paths. The path control circuit is configured to control the multipath signal transmission circuit to perform signal transmission between an upstream device and a downstream device based on a first parallel signal transmission path in the parallel signal transmission paths during a period of a handshake operation performed between the upstream device and the downstream device. The path control circuit is further configured to control the multipath signal transmission circuit to perform the signal transmission based on a second parallel signal transmission path in the parallel signal transmission paths after the handshake operation is finished.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: February 7, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Jen-Chu Wu, Ching-Jui Hsiao, Chun-Wei Chang, Sheng-Wen Chen, Ching-Chung Cheng
  • Publication number: 20230035428
    Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.
    Type: Application
    Filed: August 27, 2021
    Publication date: February 2, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Po-Jung Chou, Sheng-Wen Chen, Chung-Kuang Chen
  • Publication number: 20230021668
    Abstract: A temperature control method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: detecting a system parameter of the memory storage apparatus, and the system parameter reflects wear of a rewritable non-volatile memory module in the memory storage apparatus; determining a temperature control threshold value according to the system parameter; and performing a temperature reducing operation in response to a temperature of the memory storage apparatus reaching the temperature control threshold value to reduce the temperature of the memory storage apparatus.
    Type: Application
    Filed: August 9, 2021
    Publication date: January 26, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hung Yeh, Yun-You Lin
  • Publication number: 20230024660
    Abstract: A method for managing a memory buffer, a memory control circuit unit, and a memory storage apparatus are provided. The method includes the following steps. Multiple consecutive first commands are received from a host system. A command ratio of read command among the first commands is calculated. The memory storage apparatus is being configured in a first mode or a second mode according to the command ratio and a ratio threshold. A first buffer is configured in a buffer memory to temporarily store a logical-to-physical address mapping table in response to the memory storage device being configured in the first mode, in which the first buffer has a first capacity. A second buffer is configured in the buffer memory in response to the memory storage device being configured in the second mode, in which the second buffer has a second capacity, which is greater than the first capacity.
    Type: Application
    Filed: August 12, 2021
    Publication date: January 26, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Po-Wen Hsiao, Chun Hao Lin
  • Patent number: 11561719
    Abstract: A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 24, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Wei Lin, An-Cheng Liu, Yu-Heng Liu, Chun-Hsi Lai, Ting-Chien Zhan
  • Publication number: 20220413763
    Abstract: A mapping information management method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command instructing storing of first data from a host system; storing the first data to a rewritable non-volatile memory module according to the write command; updating mapping information corresponding to the storing of the first data; storing the mapping information to the rewritable non-volatile memory module; generating assistant information according to first part information of the mapping information, where the assistant information is not stored into the rewritable non-volatile memory module; and transmitting second part information of the mapping information and the assistant information to the host system to provide information related to the storing of the first data.
    Type: Application
    Filed: July 19, 2021
    Publication date: December 29, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chia-Hung Chien, Yi-Cheng Wu, Chia-Hsiang Cheng
  • Publication number: 20220413960
    Abstract: A crossing frames encoding management method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: reading a tag swap information corresponding to a first physical group; encoding a first data; storing a first part of the encoded first data to at least one first physical unit corresponding to a first tag information in the first physical group; and storing a second part of the encoded first data to at least one second physical unit corresponding to a second tag information in the first physical group according to the tag swap information. The first tag information corresponds to a first crossing frames encoding group. The second tag information corresponds to a second crossing frames encoding group. The first crossing frames encoding group is different from the second crossing frames encoding group.
    Type: Application
    Filed: July 15, 2021
    Publication date: December 29, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Kuang-Yao Chang, Cheng-Jui Chang
  • Patent number: 11531589
    Abstract: A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: respectively performing a single-frame decoding on a plurality of first data frames read from a physical unit set, the physical unit set contains a plurality of first physical units in a rewritable non-volatile memory module; in response to an entire decoding result of the first data frames meeting a first condition, obtaining error evaluation information related to the physical unit set, and the error evaluation information reflects a bit error status of the physical unit set; obtaining reliability information according to the error evaluation information; and performing the single-frame decoding on a second data frame read from one of the first physical units according to the reliability information.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: December 20, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Yu-Hsiang Lin
  • Publication number: 20220398155
    Abstract: A data rebuilding method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: establishing a connection between the memory storage apparatus and a host system; storing a first data to a memory of the host system via the connection; detecting an error in the first data in the memory; and rebuilding a part of data in the first data in the memory according to the error.
    Type: Application
    Filed: July 28, 2021
    Publication date: December 15, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Horng-Sheng Yan
  • Publication number: 20220365706
    Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.
    Type: Application
    Filed: June 2, 2021
    Publication date: November 17, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Wei Lin, Shih-Jia Zeng, An-Cheng Liu, Yu-Cheng Hsu
  • Publication number: 20220342765
    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes the following. When the memory storage device is powered-on, it is determined whether a power loss state of the memory storage device matches an unexpected power loss state according to a power-off instruction. Data is written into a plurality of physical programming units using a single-page programming mode and not using a multi-page programming mode when it is determined that the power loss state matches the unexpected power loss state.
    Type: Application
    Filed: June 3, 2021
    Publication date: October 27, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Publication number: 20220342547
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 27, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Yu-Cheng Hsu, Tsai-Hao Kuo, Wei Lin, An-Cheng Liu
  • Publication number: 20220334920
    Abstract: A method for managing a host memory buffer, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting whether a system abnormality occurs; copying a first command and first data corresponding to the first command stored in a data buffer of a host system to the memory storage apparatus in response to determining that the system abnormality occurs; executing an initial operation after copying the first command and the first data, wherein the initial operation initializes a part of a hardware circuit in the memory storage apparatus and does not initialize another part of the hardware circuit in the memory storage apparatus; and re-executing the first command stored in the memory storage apparatus after initializing the part of the hardware circuit.
    Type: Application
    Filed: May 3, 2021
    Publication date: October 20, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hsiao-Chi Ho