Abstract: A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip and a manufacturing method thereof are disclosed. The method includes the following steps: providing a metal carrier board having a cavity; placing a chip having a plurality of electrode pads on an active surface in the cavity of a board; filling the cavity with an adhesive for fixing the chip; forming a solder mask on the active surface of the chip and the surface of the metal carrier board at the same side, wherein the solder mask has a plurality of openings to expose the electrode pads of the chip; forming a built-up structure on the solder mask and the exposed active surface of the chip in the openings; and removing the metal carrier board. In this method the metal carrier board can support the built-up structure to thereby avoid warpage.

Abstract: A method for fabricating a multi-layer circuit board with fine pitch is provided. First, a plurality of contact pads is disposed on a core substrate. Next, a first dielectric layer, a second dielectric layer, and a third dielectric layer are formed on the core circuit board, in which a plurality of patterned openings are formed in the third dielectric layer and a plurality of vias is formed in the first and second dielectric layer, and the vias are located at the openings corresponding to the contact pads. Next, a conductive seed layer is disposed on the patterned openings and vias and a conductive layer is disposed on the conductive seed layer for forming circuit in each patterned opening and conductive via. Finally, removing the conductive layers and the conductive seed layer on the surface of third dielectric layer and forming a separation for each conductive circuit at each opening.

Abstract: A package structure with circuit directly connected to semiconductor chip, which comprises: a carrier board, a semiconductor chip, and at least a built-up structure. The carrier board is formed with a through cavity therein. The semiconductor chip is mounted in the through cavity of the carrier board, and a lateral surface of the semiconductor chip is coated by an adhesive material which is not contacted by the carrier board. The built-up structure, which includes a dielectric layer, is disposed on the surface of the carrier board and an active surface of the semiconductor chip. Part surface of the dielectric layer is exposed by the through cavity. The present invention decreases warpage of the packaging structure resulting from asymmetrical built-up structures.

Abstract: A semiconductor package structure relates to a chip-embedded semiconductor package electrically connected to a second semiconductor component. The semiconductor package structure comprises a first packaging substrate having a first surface, a second surface and at least a first cavity penetrating through the first surface and the second surface. The semiconductor package structure includes a first semiconductor component with electrode pads disposed in the first cavity. A first build-up circuit structure comprising a plurality of third and fourth conductive pads, and a second semiconductor component with electrode pads is disposed on surfaces of the third conductive pads by a first conductive element.

Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Abstract: A package substrate embedded with a semiconductor component includes a substrate, a semiconductor chip, a first dielectric layer, a first circuit layer and first conductive vias. The substrate is formed with an opening for allowing the semiconductor chip to be secured therein. The semiconductor chip has an active surface and an inactive surface, wherein a plurality of electrode pads are formed on the active surface thereof and a passivation layer disposed thereon. The first dielectric layer is disposed both on the substrate and the passivation layer, wherein vias are formed at locations corresponding to those of the electrode pads and penetrating the dielectric layer and the passivation layer to expose the electrode pads therefrom. The first circuit layer is disposed on the first dielectric layer and electrically connected to the first conductive vias.

Abstract: A package substrate embedded with a semiconductor component is provided. A semiconductor chip is received in a cavity of a substrate body, and has electrode pads on an active surface thereof. A passivation layer is disposed on the active surface and has openings for exposing the electrode pads. An electroless plating metal layer, a first sputtering metal layer and a second sputtering metal layer are sequentially formed on the electrode pads, the openings of the passivation layer and the passivation layer surface around the openings. Contact pads are formed on the second sputtering metal layer. A first dielectric layer is disposed on the substrate body and the passivation layer. A first circuit layer is formed on the first dielectric layer. First conductive vias are formed in the first dielectric layer and electrically connected to the contact pads. The first circuit layer is electrically connected to the first conductive vias.

Abstract: A chip embedded package structure and a fabrication method thereof are proposed. An adhesive layer is formed on a bottom surface of a carrier board having at least one cavity to seal one end of the cavity. At least one semiconductor chip is mounted via its non-active surface on the adhesive layer and received in the cavity. A protection layer is formed on an active surface of the semiconductor chip. A conductive layer is formed on a top surface of the carrier board, the protection layer and the cavity. A patterned resist layer is applied on the conductive layer and is formed with an electroplating opening at a position corresponding to a gap between the cavity and the semiconductor chip. An electroplating process is performed to form a metal layer in the electroplating opening, such that the semiconductor chip can be effectively fixed in the cavity by the metal layer.

Abstract: A method for fabricating an electrical conductive structure of a circuit board is disclosed. The method includes providing a circuit board having a plurality of first and second electrically conductive pads; forming on the circuit board an insulating protection layer having a plurality of openings for exposing the first and second electrically conductive pads; forming a metal adhesive layer on the first and second electrically conductive pads; forming a conductive layer on the insulating protection layer and on the metal adhesive layer formed on the first and second electrically conductive pads, the conductive layer being electrical conductive to the first and second electrically conductive pads; forming on the conductive layer a resist layer having a plurality of openings for exposing the conductive layer on the second electrically conductive pads; and electroplating a conductive structure on the conductive layer on the second electrically conductive pads exposed from the openings.

Abstract: A method for repairing a circuit board having defective pre-soldering bumps is proposed. Firstly, the circuit board having a plurality of pre-soldering bumps on a surface thereof is provided, wherein at least one of the pre-soldering bumps has a defect. Then, a micro-electroplating process or a micro-electrolyzing process is performed by a micro-electrode nearby the defective pre-soldering bump, so as to repair the defective pre-soldering bump. Therefore, the present invention is able to enhance the process yield and reduce the production cost.

Abstract: A package substrate having an electrically connecting structure are provided. The package substrate include: a package substrate substance with at least a surface having a plurality of electrically connecting pads formed thereon, allowing an insulating protective layer to be formed on the surface of the package substrate substance and the electrically connecting pads and formed with a plurality of openings corresponding in position to the electrically connecting pads so as to expose a portion of the electrically connecting pads, respectively; and a metal layer provided on an exposed portion of the electrically connecting pads, walls of the openings of the insulating protective layer, and a circular portion of the insulating protective layer encircling each of the openings thereof, and provided with a slope corresponding in position to a bottom rim of each of the openings. Accordingly, solder bleeding and short circuits are prevented.

Abstract: A manufacturing method of a solder ball disposing surface structure on a core board including: providing a core board with a first metal layer and an opposing metal bump-equipped second metal layer; forming resists on the first and second metal layers respectively; forming third, fourth and fifth openings in the resists; removing the first and second metal layers in the third and fourth openings to form first and second circuit layers and metal pads respectively; removing the metal bumps in the fifth openings to form metal flanges; removing the resists; forming first and second insulative protection layers on the first and second circuit layers and metal pads respectively; forming first and second openings in the first and second insulative protection layers to expose the first circuit layer as electrical connecting pads and expose the metal flanges respectively. Accordingly, increased contact surface area for mounting conductive elements prevents detachment thereof.

Abstract: A semiconductor package substrate includes a main body with a surface having a first circuit layer thereon and a dielectric layer covering the first circuit layer, with a plurality of vias on a portion of the first circuit layer; a plurality of first conductive vias disposed in the vias; a plurality of first electrically connecting pads on the first conductive vias and completely exposed on the dielectric layer having no extending circuits for a semiconductor chip to be mounted thereon, the first electrically connecting pad being electrically connected to the first circuit layer of the first conductive via; and an insulating protective layer disposed on the main body with an opening for completely exposing the first electrically connecting pads, whereby the circuit layout density is increased without disposing circuits between the electrically connecting pads.

Abstract: A chip embedded packaging structure includes a first metal board, a second metal board having at least a through cavity, in which the second metal board is disposed on the upper surface of the first metal board to form a heat dissipating substrate, at least a semiconductor chip and a capacitor chip embedded in the first metal board and embraced in the through cavity of the second metal board, a passive component layer disposed on part of the upper surface of the second metal board, and at least a build-up circuit layer covering the semiconductor chip, the capacitor chip, and the passive component layer and electrically connecting them through a plurality of conductive vias.

Abstract: A circuit board having a power source is provided, including: a carrier board having a first dielectric layer disposed on at least a surface thereof and a first circuit layer disposed on the first dielectric layer, wherein the first circuit layer has at least an electrode pad; a first electrode plate disposed on the electrode pad; an insulating frame member disposed on the first electrode plate, with a portion of the first electrode plate being exposed from the insulating frame member, wherein electrolyte is received in the insulating frame member and in contact with the first electrode plate; and a porous second electrode plate disposed on the insulating frame member and the electrolyte, the second electrode plate being in contact with the electrolyte, so as to provide the power source for the circuit board.

Abstract: The present invention relates to a stacked package module and a method for fabricating the same. The stacked package module comprises: a first package structure, a second package structure, a ceramic-surfaced aluminum plate, and a metal paste. Herein, the ceramic-surfaced aluminum plate has a plurality of through holes filled with the metal paste to correspond with and electrically connect the first conductive pads of the first package structure and the second conductive pads of the second package structure; and the ceramic-surfaced aluminum plate further has a first cavity to receive a chip. Besides, the present invention provides a stacked package module, which can avoid warpage, omit the process for soldering, favor the shrinkage of size and pitch of the conductive pads, and also can reduce the height of the package.

Abstract: A packaging substrate having capacitors embedded therein, comprising: two capacitor disposition layers, each respectively consisting of a high dielectric layer and two first circuit layers disposed on two opposite surfaces of the high dielectric layer, wherein each of the first circuit layers has a plurality of electrode plates and a plurality of circuits; an adhesive layer disposed between the capacitor disposition layers to adhere the capacitor disposition layers to form a core board structure, wherein spaces between the circuits of every first circuit layer are filled with the adhesive layer; and a plurality of conductive through holes penetrating the capacitor disposition layers and the adhesive layer, and electrically connecting the circuits of the capacitor disposition layers respectively; wherein, pairs of the electrode plates on the opposite surfaces of each of the capacitor disposition layers are parallel and correspond to each other to form capacitors.

Abstract: A solder ball disposing surface structure of a package substrate is disclosed, wherein a package substrate has a chip disposing surface with a first circuit layer, an opposed solder ball disposing surface with a second circuit layer, and a first insulative protection layer formed on the chip disposing surface and the first circuit layer. The solder ball disposing surface structure includes: metal pads integral to the second circuit layer; metal flanges formed around the metal pads; and a second insulative protection layer formed on the solder ball disposing surface, the second insulative protection layer having second openings each with a size smaller than an outer diameter of each of the metal flanges so as to expose a part of surfaces of the metal flanges, thereby increasing contact area of the surface for mounting conductive elements and preventing detachment of the conductive elements from the surface due to poor bonding force.

Abstract: The present invention relates to a package on package (PoP) structure, which comprises: a first packaging substrate having a plurality of conductive elements on its surface; a second packaging substrate having a plurality of conductive elements on its surface; and a surface-ceramic aluminum plate sandwiched between the first packaging substrate and the second packaging substrate. The surface-ceramic aluminum plate includes plural plated through holes extending through the layer. In addition, the first packaging substrate electrically conducts with the second packaging substrate through these plated through holes. The disclosed structure eliminates the warpage problem of PoP structure, and enhances the strength of PoP structure.

Abstract: A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder ball pads respectively, and having a first insulating passivation layer and a second insulating passivation layer respectively, wherein a plurality of first apertures and a plurality of second apertures are formed in the first insulating passivation layer and the second insulation passivation layer respectively to corresponding expose the wire bonding pads and the solder ball pads; a chemical plating metal layer formed on the wire bonding pads and solder ball pads respectively; and a wire bonding metal layer formed on a surface of the chemical plating metal layer of the wire bonding metal layer.