Abstract: A packaging substrate structure with electronic components embedded therein and a method for manufacturing the same are disclosed. The packaging substrate structure comprises: a core board; a built-up structure disposed on at least one surface of the core board, wherein the built-up structure has a plurality of conductive pads and an electronic component-disposing part on the surface thereof; a solder mask disposed on the surface of the built-up structure, where the solder mask has a open area to expose the electronic component-disposing part and a plurality of openings to expose the conductive pads of the built-up structure; and an electronic component disposed on the electronic component-disposing part and in the open area. Accordingly, the packaging substrate disclosed by the present invention exhibits enhanced electrical performance and product reliability.

Abstract: A packaging substrate is disclosed in the present invention, which includes a substrate body having a first surface and an opposite second surface. The first surface has a first cavity, and the second surface has a second cavity. The first cavity corresponds to and is interlinked to the second cavity. In order to provide a space for disposing a chip, the dimension of the second cavity is larger than that of the first cavity, such that there is a step at the interlinking region between the first cavity and the second cavity. Additionally, a plurality of wire bonding pads are disposed on the first surface around the first cavity. A package structure comprising the packaging substrate and the application thereof are also provided in the present invention.

Abstract: A packaging substrate having an electrical connection structure and a method for fabricating the same are provided. The packaging substrate have a substrate body with a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the substrate body with a plurality of openings corresponding to the conductive pads, the size of each of the openings being larger than each of the conductive pads; and electroplated solder bumps for covering the conductive pads to provide better bond strength and reliability.

Abstract: A circuit board and a method for fabricating the same are provided. The circuit board includes a core board, a first bonding layer disposed on the core board, and a first wiring layer disposed on the first bonding layer. The first bonding layer enables the first wiring layer to be bonded to the core layer better, thereby preventing delamination and forming a fine-pitch wiring layer.

Abstract: A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed.

Abstract: Provided is a circuit board including: a circuit board body with at least one surface having a plurality of electrically connecting pads; an insulating protection layer formed on the circuit board body and formed with an opening corresponding in position to one of the electrically connecting pads, being larger than the electrically connecting pad, and not being in contact with the periphery of the electrically connecting pad; and a soldering material formed on, and confined to, the electrically connecting pad; thus allowing an electrically conductive element limited in the opening formed in the insulating protection layer to be fabricated from the soldering material by a reflow process with a view to forming a fine-pitch electrically connecting structure.

Abstract: A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on the conductive film, having openings to expose parts of the conductive film. A patterned trace layer including a plurality of contact pads is formed in the openings and the blind vias to form conductive vias, with at least one contact pad electrically connected to one conductive via. A second resist is formed on the patterned trace layer without covering the contact pads. A metal barrier layer is formed on the contact pads. Finally, the first and second resists and parts of the conductive film covered the first resist are removed.

Abstract: A flip chip package structure and a method for manufacturing the same are disclosed. The method for manufacturing a flip chip package structure comprises following steps: (a) providing a semiconductor chip including a plurality of electrode pads and a plurality of first solders, and providing a packaging substrate having a plurality of conductive pads and a plurality of second solders (b) forming a resin adhesive layer on the active surface of the semiconductor chip, and the first solders are exposed from the resin adhesive layer; (c) assembling the packaging substrate and the semiconductor chip with the resin adhesive layer formed thereon to form an assembly unit; and (d) reflow soldering the assembly unit to fuse the first solders of the semiconductor chip with the second solders of the packaging substrate to form fused solders, and the packaging substrate is adhered with the resin adhesive layer.

Abstract: A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Abstract: A flip-chip package structure is disclosed, which comprises: a packaging substrate having an upper surface and a plurality of conductive pads formed on the upper surface; a semiconductor chip having an active surface and a plurality of electrode pads formed on the active surface; and a plurality of first solder bumps; wherein each first solder bump connects to an electrode pad and a conductive pad, and each first solder bump contains a solid grain.

Abstract: A heat-conductive package structure includes a carrier board having a first surface and an opposing second surface and formed with a through opening passing the carrier board; a first heat-conductive structure including a heat-conductive hole in the through opening, a first heat-conductive sheet on the carrier board, and a second heat-conductive sheet on the carrier board, wherein the first and second heat-conductive sheets are conductively connected by the heat-conductive hole; a first dielectric layer formed on the first surface of the carrier board and formed with a first opening for exposing the first heat-conductive sheet; a second dielectric layer formed on the second surface of the carrier board and formed with at least a second opening for exposing a portion of the second heat-conductive sheet; and a second heat-conductive structure formed in the second opening and mounted on the second heat-conductive sheet.

Abstract: A packaging substrate structure includes a dielectric layer with a plurality of dielectric pillars disposed on a portion of a large-dimension opening area of the dielectric layer; and a first circuit layer with a plurality of first circuits disposed on a portion of the dielectric layer, and a conductive block disposed in the large-dimension opening area of the dielectric layer having the dielectric pillars. The dielectric pillars reduce the difference of the electrical current density distribution between the large-dimension opening area and small-dimension opening areas during electroplating, thereby overcoming the conventional drawback of insufficient thickness or a hollow center of the conductive block that results in an uneven thickness of the circuit layer. The invention further provides a method of manufacturing the packaging substrate structure.

Abstract: A structure of a packaging substrate having capacitors embedded therein is disclosed. The structure comprises a core substrate, a dielectric layer, and an outer circuit layer. The core substrate comprises an inner circuit layer. The dielectric layer is disposed at both sides of the core substrate, having first conductive vias each connecting to the inner circuit layer through a piece of outer electrode plate, a piece of high dielectric material layer, a piece of inner electrode plate, and a piece of adhesive layer, in sequence. The outer circuit layer is disposed on the surface of each of the dielectric layers. Herein, the capacitor is composed of a piece of the outer electrode plate, the high dielectric material layer and the inner electrode plate. The invention further comprises a method for manufacturing the same. This can achieve low costs, avoid the formation of voids, and reduce parasitic capacitance.

Abstract: A semiconductor package substrate having electrical connecting pads includes: a substrate body having a plurality of electrical connecting pads formed on surface thereof, and a plurality of protruding lumps or concave areas of any geometric shape respectively formed on surfaces of the electrical connecting pads for increasing contact surfaces of the electrical connecting pads, thereby preventing detaching of conductive elements from surfaces of the electrical connecting pads caused by poor bonding force.

Abstract: A flip chip packaging method is disclosed. First, a substrate is provided, in which the substrate comprises a plurality of integrated circuit (IC) package substrate units therein and the surface of each IC package substrate unit comprises a plurality of connecting pads. Next, an insulating layer with patterns is formed on the substrate and the connecting pads and a plurality of openings by partially exposing the upper surface of the connecting pads. Next, a conductive material is disposed within each opening. Next, a plurality of chips is provided, in which a plurality of conductive bumps is formed over the bottom surface of the chip. Lastly, the chips are mounted over the surface of the IC package substrate unit and the substrate is separated into a plurality of flip chip package structures, in which the surface of each flip chip package structure includes at least one chip.

Abstract: A semiconductor package substrate with embedded chip and a fabrication method thereof are provided. A first insulating layer is applied on a metallic board, and formed with at least one opening for exposing a portion of the metallic board. At least one semiconductor chip is mounted on the exposed portion of the metallic board. A support plate is mounted on the first insulating layer, and formed with a through cavity at a position corresponding to the opening of the first insulating layer, for receiving the chip in the through cavity. A second insulating layer is applied on the chip and the support plate. Insulating materials of the insulating layers fill a gap between the chip and the support plate. A circuit layer is formed on the second insulating layer, wherein the circuit layer is electrically connected to the chip by conductive structures formed in the second insulating layer.

Abstract: A semiconductor device integrated with opto-electric component and method for fabricating the same provides a wafer with a plurality of optical transmitter/receiver components, and each of the optical transmitter/receiver components having an active surface and an opposite non-active surface, wherein a plurality of connecting pads and an optical active area are formed on the active surface; a dielectric layer and a circuit layer formed on the active surface, wherein the circuit layer is electrically connected to the connecting pads through electrical conductive vias formed in the dielectric layer; and an opening formed through the dielectric layer to expose the optical active area on the active surface; then an insulating layer is further formed on the circuit layer. By performing a routing process on the wafer to form a plurality of integrated devices with the optical transmitter/receiver components and circuit structures to fulfill the small and lightweight requirements of the electronic device.

Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.

Abstract: A substrate structure with embedded semiconductor chip and a fabrication method thereof are provided. The method includes: providing a carrier board having a first surface and an opposing second surface, wherein a first opening and an opposing second opening are formed in the first and second surfaces respectively, and a portion of the first opening communicates with the second opening; mounting at least one semiconductor chip to bottom of the first opening to be received in the first opening; filling an adhesive material in the first and second openings and in a gap between the chip and the carrier board to adhere the chip; forming a dielectric layer on the carrier board and the chip; and forming a circuit layer on the dielectric layer and forming conductive structures in the dielectric layer, so that the circuit layer is electrically connected to the chip via the conductive structures.

Abstract: The present invention provides a circuit board structure having an embedded capacitor and a method for fabricating the same. The circuit board structure includes a core layer board with at least one surface having non-penetrating first and second grooves, a circuit layer and a first electrode plate formed in the first and second grooves of the core layer board respectively and being flush with the core layer board; a high dielectric material layer formed on the core layer board, the circuit layer and the first electrode plate; a second electrode plate formed on the high dielectric material layer and corresponding to the first electrode plate, thereby forming a capacitor by the first and second electrode plates and the high dielectric material layer. The high dielectric material layer is formed on a plane surface so as to eliminate poor filling and improve reliability.