Abstract: A circuit board structure with optoelectronic component embedded therein comprises a carrier board with at least two through openings; a first optoelectronic component and a second optoelectronic component disposed in the openings respectively, wherein a plurality of electrode pads and optical active areas are formed on the active surfaces of the optoelectronic components; a dielectric layer formed on a surface of the carrier board and the active surface of the optoelectronic components, wherein a plurality of vias for exposing the electrode pads and two holes for exposing the optical active areas are formed in the dielectric layer; a circuit layer formed on a surface of the dielectric layer and electrically connected to the electrode pads of the optoelectronic components; an insulating protecting layer formed on the dielectric layer and the circuit layer; and at least one optical transmission element formed on a surface of the insulating protecting layer.

Abstract: A circuit board is disclosed, including a core board, wherein at least one surface thereof has a core circuit layer with a plurality of conductive lands; a first dielectric layer disposed on the core board and disposed with a plurality of openings for exposing the conductive lands; a first coupling layer disposed on the first dielectric layer, the first coupling layer having a plurality of openings disposed corresponding to the openings of the first dielectric layer; and a first circuit layer disposed on the first coupling layer and a plurality of first conductive vias disposed in the openings of the first coupling layer for electrically connecting to the conductive lands of the core circuit layer. By the formation of the first coupling layer that connects the first circuit layer and the first dielectric layer, the bond strength between the first circuit layer and the first dielectric layer is enhanced, thereby preventing detachment and delamination as encountered in the prior art.

Abstract: A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.

Abstract: Provided is a stacked semiconductor device including a first flexible layer and a second flexible layer combined together, serving as a flexible substrate body being bent somewhere such that a surface of the first flexible layer itself is face-to-face clipped, two semiconductor chips each embedded in the flexible substrate body, and an adhesive layer sandwiched in a gap between the face-to-face surface of the first flexible layer. The active surface of each of the semiconductor chips has plurality of electrode pads thereon electrically connected to a first circuit layer on the second flexible layer. The semiconductor chips are stacked up and embedded in the flexible substrate body, thereby reducing package height to achieve miniaturization of electronic products. A method for fabricating the stacked semiconductor device is also provided.

Abstract: A stack structure of a carrier board embedded with semiconductor components and a method for fabricating the same are proposed. The stack structure includes first and second carrier boards having a through hole respectively, first and second semiconductors component disposed in through holes of the first and second semiconductor components respectively, and a dielectric layer structure clamped between the first carrier board and the second carrier board and having a first dielectric layer formed on the first carrier board and an inactive surface of the first semiconductor component and filled in gaps between the first carrier board and the first semiconductor component, a second dielectric layer formed on the second carrier board and an inactive of the second semiconductor component and filled in gaps between the second carrier board and the second semiconductor component, and a bonding layer clamped between the first dielectric layer and the second dielectric layer.

Abstract: A semiconductor chip electrical connection structure includes electrode pads formed on a surface of a semiconductor chip, wherein the semiconductor chip is mounted via another surface thereof on a carrier; a plurality of conductive bumps formed on the electrode pads respectively, and exposed from a dielectric layer applied on the semiconductor chip and the carrier; and a plurality of electrical connection pads formed on the dielectric layer and electrically connected to the conductive bumps exposed from the dielectric layer so as to provide outward electrical extension for the semiconductor chip via the electrical connection pads.

Abstract: The present invention relates to a packaging substrate structure having an semiconductor chip embedded therein and a method for manufacturing the same. The structure comprises: a substrate body having a through cavity, wherein the substrate body is a multilayer board which comprises a core board and a first built-up structure disposed on each of the opposite surfaces of the core board; an semiconductor chip disposed and fixed in the cavity, wherein the active surface of the semiconductor chip has a plurality of electrode pads thereon; and a second built-up structure disposed on at least one surface of the substrate body as well as the surface of the semiconductor chip, wherein the second built-up structure has a plurality of conductive vias conducting to the first built-up structure. The present invention can reduce the stress imposed on the surface of the semiconductor chip and increase the reliability of the whole package structure.

Abstract: A manufacturing method of a solder ball disposing surface structure on a core board including: providing a core board with a first metal layer and an opposing metal bump-equipped second metal layer; forming resists on the first and second metal layers respectively; forming third, fourth and fifth openings in the resists; removing the first and second metal layers in the third and fourth openings to form first and second circuit layers and metal pads respectively; removing the metal bumps in the fifth openings to form metal flanges; removing the resists; forming first and second insulative protection layers on the first and second circuit layers and metal pads respectively; forming first and second openings in the first and second insulative protection layers to expose the first circuit layer as electrical connecting pads and expose the metal flanges respectively. Accordingly, increased contact surface area for mounting conductive elements prevents detachment thereof.

Abstract: The present invention relates to a circuit board structure with a capacitor embedded therein and the method for fabricating the same. The disclosed structure comprises: a core board; a buffer layer disposed on two surfaces of the core board and having a plurality of open areas; a first circuit layer disposed in the open areas; a high dielectric material film disposed over the first circuit layer and the buffer layer on at least one surface of the core board; and a second circuit layer disposed on the high dielectric material film, wherein the region where the second circuit layer corresponds to the first circuit layer functions as a capacitor, and the first circuit layer on two surfaces of the core board electrically connects to each other by at least one plated through hole. The present invention improves the problem of void generation and enhances the precision of the capacitor region.

Abstract: A circuit board structure of an optoelectronic component is proposed. A supporting structure has a first surface and a second surface. At least one optical transceiver has an active surface and an inactive surface. The inactive surface of the optical transceiver is mounted on the first surface of the supporting structure, and the active surface of the optical transceiver has an optical active region and a plurality of electrode pads. A dielectric layer is formed on the first surface of the supporting structure and the active surface of the optical transceiver. A circuit layer is formed on the dielectric layer and is electrically connected to the electrode pads on the active surface of the optical transceiver through the conductive structure in the dielectric layer. At least one hole, which penetrates the dielectric layer, is used to expose the optical active region on the active surface of the optical transceiver.

Abstract: A stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are proposed. A first carrier board and a second carrier board, each of which having at least one through hole, are provided. A first protecting layer and a second protecting layer are formed on a surface of the first and second carrier boards respectively. At least one first semiconductor component and at least one second semiconductor component are disposed on the first and second protecting layers and accommodated in the first and second through holes respectively. A dielectric layer is laminated between the surfaces of the first and second carrier boards without the protecting layers formed thereon. Thus, a modularized package structure with reduced space waste is formed.

Abstract: The present invention relates to a packaging substrate and a method for manufacturing the same. The packaging substrate comprises: a substrate body, wherein a surface thereof has a circuit layer comprising a plurality of circuits and a plurality of conductive pads, and the conductive pads are higher than the circuits; and an insulating protection layer disposed on the surface of the substrate body, wherein the insulating protection layer has a plurality of openings exposing the conductive pads, and the size of the openings is larger than or equal to that of the conductive pads. Accordingly, the packaging substrate structure of the present invention can be employed in a flip-chip packaging structure of fine-pitch.

Abstract: Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and second metal layer. Portions of the second metal layer are exposed from a first cavity penetrating the core layer and first metal layer. Semiconductor chips each having an active surface with electrode pads thereon and an opposite inactive surface are received in the first and second cavities and attached to the second metal layer and the first metal layer respectively. Conductive vias disposed in build-up circuit structures electrically connect to the electrode pads of the semiconductor chips. A heat-dissipating through hole penetrating the core layer and build-up circuit structures connects the metal layers and contact pads.

Abstract: A circuit board and a method for fabricating the same are disclosed. The circuit board includes: a carrier board having a circuit layer formed on at least one surface thereof; a first dielectric layer formed on the carrier board and having first openings for exposing a part of the circuit layer; conductive vias formed in the first openings; a second dielectric layer formed on the first dielectric layer and having second and third openings formed therein, wherein the second openings correspond to the first openings for exposing the conductive vias; and a multi-layered metal electroless plating circuit layer formed in the second and third openings for electrically connecting the circuit layer of the carrier board via the conductive vias, thereby allowing the multi-layered metal electroless plating circuit layer to be embedded into the first and second dielectric layers to enhance the bonding strength therebetween and increase the reliability of the circuit board and facilitate formation of fine circuits.

Abstract: A circuit board structure and a fabrication method thereof are disclosed. The circuit board structure includes a carrying board having a first and an opposite second surface and having at least one through cavity formed therein; a semiconductor chip disposed in the through cavity of the carrying board; an adhesive material filling the gap between the through cavity of the carrying board and the semiconductor chip to fix the semiconductor chip in the through cavity; and a reinforcing layer disposed on the second surface of the carrying board and the inactive surface of the semiconductor chip, thereby increasing the strength of the carrying board as well as the reliability of the circuit board.

Abstract: A circuit board disclosed in the present invention includes a core board on which a first circuit layer is placed, wherein the first circuit layer has a plurality of conductive pads; and at least one built-up structure covering the surface of the circuit board, which comprises a dielectric layer, a second circuit layer, and a plurality of conductive vias without being surrounded by annular metal rings. The conductive vias are conducted with the conductive pads of the first circuit layer and the second circuit layer. Besides, the surface of the second circuit layer is in the same height as the surface of the dielectric layer. Also, the present invention provides a method for manufacturing the above-mentioned circuit board structure. Therefore, a circuit board having fine circuits can be formed, and the shape of the circuit can be ensured efficiently. Moreover, electric performances of the circuit board can be improved.

Abstract: A packaging substrate structure with an electronic component embedded therein and a fabricating method thereof are disclosed. The packaging substrate structure comprises a core plate; a first built-up structure disposed on a surface of the core plate and comprising a first dielectric layer and a first circuit layer disposed on the first dielectric layer; a second built-up structure disposed on the first built-up structure, wherein a cavity is disposed in the second built-up structure to expose the first built-up structure; an electronic component disposed in the cavity, wherein the electronic component has an active surface having a plurality of electrode pads and an inactive surface facing the first built-up structure; and a solder mask disposed on the surfaces of the second built-up structure and the electronic component, and having a plurality of first openings to expose the electrode pads of the electronic component.

Abstract: A packaging substrate structure with electronic components embedded therein and a method for fabricating the same are disclosed. The packaging substrate structure comprises a core board with a wiring layer on the two opposite surfaces thereof; a first built-up structure disposed on at least one surface of the core board and having a cavity to expose the surface of the core board; an electronic component disposed in the cavity and having an active surface and an inactive surface, where the active surface has pluralities of electrode pads and the inactive surface faces the surface of the core board; and a solder mask disposed on the surfaces of the first built-up structure and the electronic component, where the solder mask has pluralities of first openings to expose the electrode pads of the electronic component. Accordingly, the packaging substrate disclosed by the present invention can efficiently enhance electrical performance and product reliability.

Abstract: A semiconductor package structure relates to a chip-embedded semiconductor package electrically connected to a second semiconductor component. The semiconductor package structure comprises a first packaging substrate having a first surface, a second surface and at least a first cavity penetrating through the first surface and the second surface. The semiconductor package structure includes a first semiconductor component with electrode pads disposed in the first cavity. A first build-up circuit structure comprising a plurality of third and fourth conductive pads, and a second semiconductor component with electrode pads is disposed on surfaces of the third conductive pads by a first conductive element.

Abstract: A circuit board having an electrically connecting structure and a method for fabricating the same are provided. A circuit board body having inner-layer circuits is provided. A circuit layer is formed on at least an outermost surface of circuit board body, and including electrically connecting pads and circuits. The electrically connecting pads are partially electrically connected to the circuits, and are partially electrically connected to the inner-layer circuits via conductive vias. An insulating protective layer is disposed on the circuit board body and is formed with openings therein for exposing the electrically connecting pads. Conductive posts are formed on the electrically connecting pads. Standalone metal pads are formed on the insulating protective layer but are not used for electrical connection.