Abstract: A high speed test system for performing tests on various electrical devices including integrated circuits and semiconductor wafers at device operating speeds in the Gigahertz range. The test system including a test head having a test platform for receiving an adapter board that holds the device under test. The test platform is exposed on one side of the test head to facilitate readily changing the tested devices and easy coupling with conventional wafer prober machines. A plurality of pin driver boards are positioned radially about the test platform to minimize the distance between the device under test and the pin driver boards. Electrical signals presented at specific locations on the device under test are measured in response to the inputted signals form the pin drivers using an electro-optic sensor preferably located central of the pin driver boards and within 1.0 cm of the device under test to minimize pin capacitance.