Patents Assigned to PMC-Sierra
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Patent number: 9215062Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.Type: GrantFiled: July 3, 2015Date of Patent: December 15, 2015Assignee: PMC-Sierra US, Inc.Inventors: Hormoz Djahanshahi, William Michael Lye, Mark Hiebert, Rod Zavari
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Patent number: 9208018Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.Type: GrantFiled: March 15, 2013Date of Patent: December 8, 2015Assignee: PMC-Sierra, Inc.Inventors: Philip Lyon Northcott, Peter Graumann, Stephen Bates
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Patent number: 9197318Abstract: A method and apparatus for modulating a beam from a laser with an electro-absorption modulator, and determining the optical power of the beam by measuring a back current produced by the electro-absorption modulator. The apparatus comprises an electro-absorption modulator and a back current detector. The electro-absorption modulator receives an electronic digital signal from an electro-absorption driver. The electro-absorption modulator modulates the beam of the laser according to the electronic digital signal. While modulating the beam, the electro-absorption modulator produces a back current. This back current is proportional to the optical power of the beam. The back current detector measures the back current to determine the optical power of the beam.Type: GrantFiled: June 7, 2013Date of Patent: November 24, 2015Assignee: PMC-SIERRA US, INC.Inventor: Paulius Mosinskis
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Patent number: 9183085Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Predefined gears correspond to different predefined ECC schemes. Based on an observed bit error rate, a gear from a set of predefined gears is selected for use for a particular region of memory. Each gear of the set of predefined gears includes a lower-latency ECC decode option and one or more higher-latency ECC decode options.Type: GrantFiled: May 22, 2012Date of Patent: November 10, 2015Assignee: PMC-Sierra, Inc.Inventor: Philip L. Northcott
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Patent number: 9176812Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Data is stored in page stripes. The page stripes can have varying amounts of payload capacity based on selected error correction code strength. Allocation blocks can be divided into journaling cells, correspond to minimum units of data for which a journaling engine or flash translation layer has a logical-to-physical mapping.Type: GrantFiled: May 22, 2012Date of Patent: November 3, 2015Assignee: PMC-Sierra, Inc.Inventors: Philip L. Northcott, Peter Dau Geiger, Jonathan Sadowsky
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Patent number: 9170876Abstract: A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of secondary codewords is read from the second memory and decoded, utilizing a hard-decision decoder, to identify and correct errored data bits in the each secondary codeword and to determine a location of each errored data bit in the primary codeword. An adjusted LLR vector is generated by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.Type: GrantFiled: December 31, 2013Date of Patent: October 27, 2015Assignee: PMC-Sierra US, Inc.Inventors: Stephen Bates, Peter Graumann, Philip Lyon Northcott, Sean Gregory Gibb
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Patent number: 9166623Abstract: A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.Type: GrantFiled: March 14, 2013Date of Patent: October 20, 2015Assignee: PMC-Sierra US, Inc.Inventors: Stephen Bates, Peter Graumann, Phil Northcott
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Patent number: 9160673Abstract: A method is provided for selecting a transmit link in a bonding group. Traffic is distributed to the links based on a selection method. Typical selection methods for bonded links of the same type include round robin or weighted round robin. A method is disclosed including selecting from among bonded links of different types based on link priority or link-to-group backpressure, sometimes both, and in some cases also based on traffic class. Link priority is based on the reliability, or quality, of the link. Adding link priority, and optionally traffic class, into the selection method allows high priority traffic to be always transported over high quality links. Also, considering the link-to-group backpressure, such as based on congestion status of operational links, or active links, will help avoid link congestion. The method is relevant to Quality of Service (QoS) implementation in transportation systems used for mobile backhaul or carrier access networks.Type: GrantFiled: February 28, 2013Date of Patent: October 13, 2015Assignee: PMC-Sierra US, Inc.Inventors: Tao Lang, Avi Hagai, Nadav Busani, Amit David
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Patent number: 9146890Abstract: A system and method are disclosed for a flexible routing engine in a PCIe switch. The system may include a switch manager that is enabled, through firmware, to configure one or more routing tables associated with a switch stack of a PCIe switch. To enable non-transparent bridging and non-standard routing, such as mapped I/O routing, the method may include receiving a transaction layer packet at a mapped I/O routed port of a PCIe switch, and performing translation of the requester ID of the packet utilizing tables that are updated by the firmware of the switch manager to route the packet through the switch.Type: GrantFiled: January 25, 2013Date of Patent: September 29, 2015Assignee: PMC—SIERRA US, INC.Inventors: David Alan Brown, Peter Z. Onufryk
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Patent number: 9148146Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.Type: GrantFiled: May 20, 2013Date of Patent: September 29, 2015Assignee: PMC-Sierra, Inc.Inventors: Julien Faucher, Michael Ben Venditti
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Patent number: 9143371Abstract: A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.Type: GrantFiled: July 15, 2013Date of Patent: September 22, 2015Assignee: PMC-Sierra US, Inc.Inventor: William D. Warner
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Patent number: 9128858Abstract: Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.Type: GrantFiled: January 29, 2013Date of Patent: September 8, 2015Assignee: PMC-SIERRA US, INC.Inventors: Rino Micheloni, Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser
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Patent number: 9130650Abstract: This disclosure provides methods and apparatus for processing differential signals having non-inverted and inverted signals. An example apparatus has first and second circuit arms, each arm connected to receive one of the input signals. Each arm has a post-cursor branch comprising a delay, an inverter and a series terminating resistance connected between the first input and a first circuit arm common node, and a main cursor branch comprising a buffer and a series terminating resistance connected between the first input and the first circuit arm common node. A first transformer has a primary winding connected between the first circuit arm common node and a first output and a secondary winding connected between an output of the buffer of the main cursor branch of the second arm and ground, with a capacitor and a resistor connected in series between the secondary winding and ground.Type: GrantFiled: October 31, 2013Date of Patent: September 8, 2015Assignee: PMC-SIERRA US, INC.Inventor: Predrag Acimovic
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Patent number: 9124287Abstract: An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs.Type: GrantFiled: December 22, 2014Date of Patent: September 1, 2015Assignee: PMC-SIERRA US, INC.Inventors: Stanley Ho, William Michael Lye
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Patent number: 9118511Abstract: A distributed Analog Finite Impulse Response (AFIR) filter circuit with n physical taps provides an output equivalent to an AFIR filter circuit with 2n?1 taps by emulating n?1 taps. An impedance mismatch, with respect to the characteristic impedance of the input and output transmission lines, is imposed at the input and output terminals to take advantage of the resulting reflective signal paths, which emulate the additional taps. This implementation results in space-savings and power-savings for on-chip implementations of the circuit. Implementations disclosed herein are advantageous in telecommunication applications that rely heavily on copper/FR4 backplanes in serial data links.Type: GrantFiled: October 9, 2013Date of Patent: August 25, 2015Assignee: PMC-Sierra US, Inc.Inventor: Johannes G. Ransijn
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Patent number: 9112517Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.Type: GrantFiled: June 4, 2014Date of Patent: August 18, 2015Assignee: PMC-Sierra US, Inc.Inventors: William Michael Lye, Hormoz Djahanshahi, Mark Hiebert, Rod Zavari
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Patent number: 9104825Abstract: A method of reducing current leakage in product variants of a semiconductor device, during the fabrication of the semiconductor device. The method involves using a semiconductor process technique for reducing current leakage in semiconductor product variants having unused circuits. A semiconductor device or integrated circuit fabricated by this method has reduced current leakage upon powering as well as during operation. The method involves semiconductor process technique that substantially increases the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors.Type: GrantFiled: September 22, 2014Date of Patent: August 11, 2015Assignee: PMC-Sierra US, Inc.Inventors: Bruce Scatchard, Chunfang Xie, Scott Barrick, Kenneth D. Wagner
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Patent number: 9094033Abstract: A device that performs Quantization Noise-Shaping and operates at high clock rates. The device can be implemented in parallel with large parallelization factors to produce extremely high throughput. The device has two feed-forward filters that can be implemented using standard parallel Digital Signal Processing techniques. The device can be used in various systems such as Digital-to-Analog Converter (DAC) system and Fractional-N frequency synthesis systems.Type: GrantFiled: January 23, 2015Date of Patent: July 28, 2015Assignee: PMC-Sierra US, Inc.Inventor: William Michael Lye
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Patent number: 9092353Abstract: Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.Type: GrantFiled: January 29, 2013Date of Patent: July 28, 2015Assignee: PMC-SIERRA US, INC.Inventors: Rino Micheloni, Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser
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Patent number: 9091711Abstract: A method and system are disclosed which determine a frequency offset between a reference clock frequency of a receiver and a transmit clock frequency embedded in a received non-return to zero (NRZ) signal. A polarity of the frequency offset is determined based on a moving direction of a sampling clock edge relative to an edge of a signal eye of the received NRZ signal and a region of the signal eye containing the sampling clock edge. A magnitude of the frequency offset is determined based on a time taken by the sampling clock edge to sweep the signal eye.Type: GrantFiled: July 18, 2013Date of Patent: July 28, 2015Assignee: PMC-Sierra US, Inc.Inventor: Nanyan Wang