Abstract: The present disclosure provides methods and apparatus for dynamically adjusting the common mode voltage at the LC tank node and/or the power supply voltage of a VCO with an LC resonator in order to force oscillation start-up by temporarily increasing gain. Methods according to certain preferred embodiments may reduce power consumption and/or overcome threshold voltage limitations and/or increase frequency and frequency tuning range during normal (steady-state) operation.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: An oscillator and method for generating a signal are provided. The oscillator comprises an electro-mechanical resonator and a reconfigurable oscillator driver. The reconfigurable oscillator driver starts the oscillator in single-ended mode to avoid latching and transitions the oscillator to differential mode in such a manner as to sustain oscillations therein. The reconfigurable oscillator driver comprises two back-to-back banks of inverters and an adjustable feedback resistor. In single-ended mode, one bank is disabled and the other bank is enabled. To transition to differential mode and improve the quality of the signal, the number of enabled inverters is equalized in both banks.

Abstract: Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A Mueller-Muller circuit obtains timing information for a received signal in which the receiving device samples the signal once per baud period.

Abstract: The present disclosure provides a means to adjust the relative location of output rising and falling transitions to reduce single-ended duty cycle distortion (DCD) effects in the output data stream originating from the transmitter data path. This serves to improve high-speed single-ended signal characteristics and reduce electromagnetic interference (EMI). Another feature enabled by embodiments of the present disclosure is polarity skew (also referred to as differential skew) reduction between transmitter outputs. In an embodiment, the disclosed method and apparatus for transmitter data path single-ended DCD correction describes a closed-loop calibration system including the actuation apparatus within the transmitter, a sensing block at the output of the transmitter to measure the amount of single-ended DCD, and a calibration block operating on the sensor output to devise correction control inputs to the actuator in the transmitter to correct the data path single-ended DCD present.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. A page is associated with a set of primary ECC codewords, and a page stripe is associated with a set of secondary codewords and primary over secondary parity (PoSP) ECC codewords. Two or more page stripes can form a page grid, wherein the page grid is associated with a group of tertiary ECC codewords, wherein the last page stripe of the page grid has a reduced payload capacity.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: A method and apparatus are provided for multiplexing one or more Low-Order (LO) ODUj/ODUflex clients into a High-Order (HO) ODUk in an Optical Transport Network (OTN). LO bytes are multiplexed in accordance with a tributary slot assignment for a selected LO ODUj of the HO ODUk stream using a permutation matrix. In an implementation, each byte on each ingress port of a W-port space-time-space switch is configurably assigned to an associated timeslot of an associated egress port, using time-division multiplexing. The number of TribSlots assigned to an ODUflex may be increased and decreased hitlessly. A Clos-like Space-Time-Space switch is used to interleave bytes from Low-Order ODUk words into High-Order ODUk words.

Abstract: A power-saving method for a first-in-first-out (FIFO) buffer implemented in a memory. The memory is segmented into a plurality of logical segments. For each logical segment, for each power saving mode, a recovery time and recovery overhead to an operational mode, and a transition overhead for transitioning the logical segment into the power saving mode, are determined. During each clock cycle, a determination is made as to whether a net power saving will result by entering each logical segment into a power saving mode based on a minimum time before a read or write pointer will enter the logical segment as well as the recovery time, the recovery overhead, and the transition overhead. The logical segment is transitioned to the power saving mode only if a net power saving will result, and is returned to the operational mode when the minimum time is no longer greater than the recovery time.

Abstract: A high efficiency search table is implemented with a multiple hash algorithm. The search table allows for exact match searching of arbitrary data sets with fixed latency. The probability of collisions from the hash algorithms is reduced through the use of oversized pointer tables allowing for a level of indirection between hash values and table entries. In the event of a collision in all hash functions, a firmware assisted cuckoo algorithm is employed to resolve the collision.

Abstract: A distributed electrostatic discharge (ESD) protection circuit is provided. At frequencies beyond 10 GHz, the parasitic capacitance of primary ESD protection voltage clamping devices, such as diodes, hampers adequate insertion and return loss, in spite of lumped inductor tuning. An ESD protection circuit according to an embodiment of the present disclosure solves the problem by distributing the diode, or voltage clamping device, capacitance among several sections of an artificial transmission line. The power and ground ESD return paths are also distributed to ensure a constant current density in the voltage clamping segments, even for fast charged-device model (CDM) discharge events. By sharing the ESD return paths between differential inputs (or outputs), these return paths have no impact on differential return or insertion loss.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.

Abstract: A SerDes receiver comprising: an input for receiving a signal, the signal having a baud rate; an Analog Finite Impulse Response equalizer (AFIR) for equalizing the received signal, the AFIR comprising: a pre-cursor tap having a pre-cursor coefficient; a cursor tap having a cursor coefficient, the cursor coefficient being constrained to a non-negative value; and a post-cursor tap having a post-cursor coefficient; an adaptation block coupled to the AFIR, the adaptation block configured to adjust the pre-cursor coefficient and the post-cursor coefficient based on the received signal, the adaptation block further being configured to constrain the values of the pre-cursor and post-cursor coefficients to be non-positive.

Abstract: This disclosure describes a method and apparatus for signaling the phase and frequency of OTN and Constant Bit Rate (CBR) clients in an OTN network. The principles discussed are applicable when multiple stages of OTN multiplexing and demultiplexing are utilized. They are also applicable for use with the Generic Mapping Procedure (GMP) and Asynchronous Mapping Procedure (AMP). A method to use the phase and frequency of an ODUk/ODUflex to adjust a local reference clock to enable the recovery of the phase and frequency of a CBR client demapped from the ODUk/ODUflex is described.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Both primary parity symbols for primary codewords and secondary parity symbols for secondary codewords are generated. The secondary parity symbols are spread out across each page of a group of pages.

Abstract: A method and apparatus for timing optimization are disclosed, which rely on information gathered from a timing detection circuit to find the optimal sampling point of a data recovery system. In an implementation, a timing shift is optimized based on Gardner detector data. In an example, a Gardner detector, or an early and late extraction portion thereof, is added to the data path, and the data path clock is shifted so that it is centered on the data transition mean. In an implementation, the sampling point of the data path is optimized for better horizontal eye opening using a Gardner detector's output for centering the average crossing point of different paths. In an example embodiment, an apparatus is provided with a second clock recovery that is not completely independent of a first clock recovery.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Abstract: A system and method for automatically generating a test script includes receiving a test case flow that includes steps, nodes, and sub-nodes, wherein each sub-node is associated with a use-case based application programming interface (UC-API), for each sub-node of the test case flow retrieving a template array corresponding to the UC-API associated with the sub-node, generating a test array wherein for each node in a step, generating a node array wherein the elements of each node array includes the sub-node arrays associated with the sub-nodes of the node, for each step, generating a step array wherein the elements of each step array include references to the node arrays of the nodes in the step, and populating the test array wherein each element of the test array includes one of the step arrays.