Abstract: Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable gain amplifier (VGA), and can introduce significant nonlinearities, a problem exacerbated by signals with a large peak-to-average ratio (PAR). One embodiment provides feed forward information from the VGA regarding its status to a DFE, and the DFE adjusts its filtering based on the provided information. The advantages are also applicable to fixed-gain amplifiers and to transversal filters.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: Apparatus and methods mitigate a problem of equalizing communications signals that have been distorted by severe non-linearities such as clipping or harsh compression. For example, severe non-linearity occurs when signal compression or signal clipping occurs at rates above 20% of the data transmission interval. Severe non-linearities may significantly reduce system performance. Disclosed techniques selectively apply DSP equalization based on the detection of non-linearity for a present sample or one or more samples prior to the present sample. These techniques can be implemented in relatively low-cost high-speed SerDes designs to improve eye openings and reduce sensitivity to InterSymbol Interference (ISI) and to improve bit error rate (BER).

Abstract: A system and method are disclosed for a flexible routing engine in a PCIe switch. The system may include a switch manager that is enabled, through firmware, to configure one or more routing tables associated with a switch stack of a PCIe switch. To enable non-transparent bridging and non-standard routing, the method may include receiving a transaction layer packet at a translated routing port of a PCIe switch, and performing translation of the address and requester ID of the packet utilizing tables that are updated by the firmware of the switch manager to route the packet through the switch.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

Abstract: A method and apparatus are provided for generating Generic Mapping Procedure (GMP) stuff/data decisions, which avoids brute force modulo arithmetic and is efficient for hitless adjustment of ODUFIex (G.7044) in an Optical Transport Network (OTN). Addition operations are used, rather than multiplication operations, to facilitate faster and less computationally expensive calculation of data/stuff decisions, based on calculated residue values. Residue values are logically arranged in rows to facilitate residue calculation, such as based on relationships with previously calculated residue values. This method is also applicable for mapping and de-mapping Constant Bit Rate (CBR) clients into and from an ODUk carrier.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein a layer specific attenuation factor is provided for each layer of the LDPC parity check matrix. An attenuation factor matrix comprising a plurality of coefficients specifies the specific attenuation factor for each layer and each iteration of the decoding process. A check node processor performs check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing the normalized layered min-sum algorithm wherein the attenuation factor of the min-sum algorithm is determined by the coefficients of the attenuation factor matrix.

Abstract: Methods and circuits for equalizing a linear response in an observation path of a digital pre-distorter. A method comprises generating observed signals in an observation path based on observing a transmit signal; down-converting the observed signals into intermediate frequencies using different LO frequencies; calculating a ratio using the intermediate frequencies; and equalizing the linear response of the observation path on the observed signals using the ratio. An apparatus comprises a directional coupler for observing a transmit signal and generating observed signals; a down-converter for converting the observed signals into intermediate frequencies using different LO frequencies; and an adaptive estimator for calculating a ratio using the intermediate frequencies and using the ratio to equalize a linear response from the observation path on the observed signals.

Abstract: A method for estimating a carrier frequency offset over a dispersive but spectrally flat channel comprises determining an autocorrelation of a received oversampled complex baseband digital signal, and estimating the carrier frequency offset based on an angle of the determined autocorrelation.

Abstract: A low-density parity check (LDPC) decoder is provided that eliminates the need to calculate customized check node codeword estimates by considering the check node processor and the variable node processor as a single processer having a shared memory for storing common variables to be used during both the check node processing and the variable node processing of the iterative decoding method.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are rearranged during the decode process in an attempt to avoid error mechanisms brought about by the iterative nature of the LDPC belief propagation decoding process, such as stopping sets and trapping sets.

Abstract: A self-synchronous scrambler/descrambler and method for operating same are disclosed. A self-synchronous scrambler/descrambler comprises an M-bit Scrambler State memory for retaining M previously scrambled/descrambled bits, a SOP/EOP Zero Inserter for receiving replacing certain bytes of the bus word with a value of zero, a Mid-Packet Word Logic for scrambling/descrambling the received bits using the previously scrambled/descrambled bits from the M-bit Scrambler State memory; and a Barrel Shifter for rotating the M-bit Scrambler State memory backwards. The method for scrambling/descrambling bits, comprising receiving a bus word, replacing certain bytes of the bus word, scrambling/descrambling bits of the bus word by exclusive-ORing with previously scrambled/descrambled bits, retaining the scrambled/descrambled bits of the bus word; and rotating the scrambled/descrambled bits of the bus word backwards an amount.

Abstract: A method and system are provided for performing Decision Feedback Equalization (DFE) and Decision Feedback Sequence Estimation (DFSE) in high-throughput applications that are not latency critical. In an embodiment, overlapping blocks of samples are used to allow for the parallelization of the computation and the breaking of the critical path. In addition, the overlap of the windows addresses issues associated with performance loss due to what is termed “ramp-up” and “ramp-down” BER loss.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Abstract: Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP structure for the implementation of the DSP functions in the control loop for use in an ASIC and requires a reduced DSP clock rate, which in turn reduces the need for pipelining and/or high-speed libraries. Thus lower latency, better tracking performance and lower power consumption are achieved. An example embodiment involves splitting the timing error signal, supplied at a given update rate, into a sum and a difference component, and processing each component in separate circuit chains at half the update rate. The resultant half-rate control signals from each separate circuit chain are joined to provide a control signal at the full update rate. Thus, implementations of the present disclosure perform like a full-rate structure, but require a halved DSP clock rate.

Abstract: A method of background calibration of aperture center errors in a data communication system is provided. In an implementation, in response to detection of a low sampler output (“0”) in between two high sampler outputs (“1”), the method includes: determining a direction of an ADC output signal at the time of the detected low output; and adjusting timing at a selected sampler based on the determined signal direction. In an example implementation, the method includes watching for bubbles in the thermometer code output, and estimating the first derivative of the signal at the time of the bubble, then estimating the sign of the errors. In an example implementation, the errors are used in a control loop to reduce the aperture center error.

Abstract: Methods and apparatus improve the signal integrity of high-speed integrated circuits. Disclosed is a passive network for an input to a receiver. One embodiment of the passive network has two coupled inductors to improve both return loss and insertion loss characteristics. A shunt inductor is connected in series with the termination resistance, while a series inductor is placed in series between the pad and receiver circuitry. By exploiting deliberately-introduced mutual coupling between these two inductors, an area-efficient passive network is created that improves both the return loss and input bandwidth.

Abstract: A method and apparatus to digitally remove in-band non-linear signal distortion caused by a radio frequency (RF)/intermediate frequency (IF) receiver circuit that has non-linearities, which are further affected by low-IF ADC sample aliasing.

Abstract: A link negotiation method for enabling communication between first and second Serial Attached Small Computer Interface (SAS) storage devices operably coupled by an optical cable. The method includes continuously transmitting a non-SAS data pattern between the first and second SAS storage devices. In response to successful exchange of the non-SAS data between the first and second SAS storage devices, a SAS data pattern is continuously transmitted between the first and second SAS storage devices. In response to successful exchange of the SAS data pattern between the first and second SAS storage devices, an initial frame is continuously transmitted between the first and second SAS storage devices. Communication between the first and second SAS storage devices is enabled in response successful communication of the initial frame between the first and second SAS storage devices.