Abstract: A process for preparing a metallic interconnecting plug in a semiconductor device which comprises the steps of: i) forming an insulating layer on the surface of a semiconductor substrate or a metal underlayer of the semiconductor device, ii) forming a hole in the insulating layer to expose the surface of the semiconductor substrate or the metal underlayer, iii) exposing the surface of the insulating layer to the vapor of a blocking agent under a pressure ranging from 10.sup.

Abstract: A liquid organocuprous compound of formula (I) of the present invention can be conveniently used in a low-temperature CVD process for the production of a contaminant-free copper film having good step-coverage and hole-filling properties: ##STR1## wherein: R.sup.1 represents a C.sub.3-8 cycloalkyl group, andR.sup.2 and R.sup.3 are each independently a perfluorinated C.sub.1-4 alkyl group.

Abstract: A circuit for selectively generating one of three voltage level as an output has a pull-up transistor and a pull-down transistor. The circuit includes a bias voltage source for generating a constant voltage signal; a temperature compensating constant-current source for outputting variable voltage signal corresponding to a temperature change; a tri-state control circuit for receiving a data signal to generate a control signal based on the data signal; and a switching circuit, in response to the control signal, for selectively the bias voltage source and the temperature compensating constant current source to the pull-up and pull-down transistors.

Abstract: Flash EEPROM memory devices having mid-channel injection characteristics include a substrate having source and drain regions of first conductivity type therein extending adjacent a surface thereof. A stacked-gate electrode is also provided on the surface, between the source and drain regions. To provide improved mid-channel injection characteristics during programming, a preferred semiconductor channel region is provided in the substrate at a location extending opposite the stacked-gate electrode. This channel region comprises a first "source-side" region of second conductivity type (e.g., P+) and a second "drain-side" region of predetermined conductivity type (e.g., P-, N-). The second region has a lower first conductivity type dopant concentration therein than the drain region and a lower second conductivity type dopant concentration therein than said first region, and more preferably has a lower second conductivity type dopant concentration therein than said substrate.

Abstract: A temperature compensatory constant current generator comprises a temperature inversely proportional constant current generator for supplying a temperature inversely proportional current, a temperature proportional constant current generator for supplying a temperature proportional current, a temperature inversely proportional current supplier for outputting the temperature inversely proportional current from the temperature inversely proportional constant current generator, a temperature proportional current supplier for outputting the temperature proportional current from the temperature proportional constant current generator and a square root generator for providing a current proportional to multiplied square roots of the temperature inversely proportional current and the temperature proportional current.

Abstract: A new Bcl-2 related gene "Bfl-1", a polypeptide encoded by said gene, and a plasmid and a transformant comprising said gene are disclosed. The gene can be used to detect cancer.

Abstract: An adaptive biasing circuit is combined to a fully differential cascode operational amplifier ("OP AMP") to eliminate the effect of a slew rate, thereby increasing the operation speed of the OP AMP while maintaining a high DC voltage gain. A common mode feedback circuit with a large input common mode voltage range is also connected to the OP AMP, thereby maximizing a linear output voltage swing range. The common mode feedback circuit comprises a nMOS input stage differential amplifier and a pMOS input stage differential amplifier which are connected in parallel, and a push-pull CMOS amplifier for converting current outputs from the nMOS and the pMOS input stage differential amplifiers to an output voltage signal. The adaptive bias circuit comprises an operational transconductance amplifier, two current subtractor circuits and four output transistors.

Abstract: A high power waveguide valve capable of selectively transmitting or sealing the high power without causing its breakdown during a high power operation is disclosed. The inventive high power waveguide valve includes a vacuum chamber, a U-shaped waveguide being provided in the vacuum chamber, a first linear motion driver for vertically sliding the U-shaped waveguide, a dual H-corners assembly connected with the U-shaped waveguide, a sealing plate for selectively sealing the radio frequency between the U-shaped waveguide and the dual H-corners assembly, and a second linear motion driver for horizontally sliding the sealing plate.