Abstract: A production schedule estimation method and a production schedule estimation system are provided. The production schedule estimation method includes the following steps. Current-day work-in-process data, machine group cycle time data of a machine group, and productivity data of the machine group are obtained. The current-day work-in-process data, the cycle time data of the machine group, and the productivity data of the machine group are inputted into a prediction model. Current-day cycle time data and a current-day move volume for each of multiple stations in the machine group are calculated through the prediction model. And, current-day move data is calculated according to the current-day cycle time data and the current-day move volume for each of the multiple stations in the machine group.

Abstract: A phase shift mask suitable for forming a via pattern on a transferred object is provided. The phase shift mask has a first pattern region and a second pattern region. The phase shift mask includes a substrate and a phase shift pattern layer. The phase shift pattern layer is located on the substrate and is disposed corresponding to one of the first pattern region and the second pattern region. An optical phase difference corresponding to the first pattern region and the second pattern region is basically 180 degrees. The first pattern region has a via region away from the second pattern region. The second pattern region includes a plurality of strip patterns surrounding the via region.

Abstract: A memory structure including a substrate and memory cells is provided. The memory cells are stacked on the substrate. Each memory cell includes a first conductive layer, a first gate, a second gate, a second conductive layer, a channel layer, and a first charge storage layer. The first conductive layer, the first gate, the second gate, and the second conductive layer are sequentially stacked. The first conductive layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductive layer are electrically insulated from each other. The first gate and the second gate are electrically insulated from the channel layer. The first conductive layer and the second conductive layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

Abstract: A sub-sense amplifier includes a semiconductor substrate, a first pair of complementary transistors, a second pair of complementary transistors, and at least one ground transistor. The first pair and second pair of complementary transistors and the ground transistor are formed on the semiconductor substrate. The first pair of complementary transistors are disposed in line symmetry with a center line of the sub-sense amplifier as a symmetry axis, and gates of the first pair of complementary transistors are coupled to a node. The second pair of complementary transistors are also disposed in line symmetry with the center line, wherein the current directions of the second pair of complementary transistors are the same. Sources and drains of the first pair of complementary transistors are coupled to gates and sources of the second pair of complementary transistors, respectively. The ground transistor connects in series with the second pair of complementary transistors.

Abstract: A backside illuminated image sensor, including a semiconductor layer, a first gate structure, and a light sensing device, is provided. The semiconductor layer has a first surface and a second surface opposite to each other. The first gate structure is disposed on the second surface. The light sensing device is located in the semiconductor layer. The light sensing device extends from the first surface to the second surface.

Abstract: A ferroelectric memory structure including a first conductive line, a second conductive line, and a memory cell is provided. The second conductive line is disposed on the first conductive line. The memory cell is disposed between the first and second conductive lines. The memory cell includes a switch device and a ferroelectric capacitor structure. The switch device is disposed between the first and second conductive lines. The ferroelectric capacitor structure is disposed between the first conductive line and the switch device. The ferroelectric capacitor structure includes ferroelectric capacitors electrically connected. Each of the ferroelectric capacitors includes a first conductive layer, a second conductive layer, and a ferroelectric material layer. The second conductive layer is disposed on the first conductive layer. The ferroelectric material layer is disposed between the first conductive layer and the second conductive layer.

Abstract: A manufacturing method of a semiconductor device at least includes the following steps. A substrate having a stacked structure is provided. An epitaxy process is performed to form an epitaxial layer on the substrate on two sides of the stacked structure. A recess is forming on the two sides of the stacked structure, wherein the recess penetrates through the epitaxial layer, extends into the substrate, and has a tip located in the substrate. A source/drain region is formed in the recess, wherein a material of the source/drain region comprises silicon germanium. A spacer wall material layer is formed on the substrate. A portion of the stacked structure is removed to from a gate structure. A portion of the spacer wall material layer is removed to form a spacer wall on the epitaxial layer. A semiconductor device is also provided.

Abstract: A wafer structure and a manufacturing method thereof are provided. The wafer structure includes a substrate structure, a first dielectric layer, multiple test pads, a second dielectric layer, and multiple bond pads. The first dielectric layer is disposed on the substrate structure. The test pads are disposed in and exposed outside the first dielectric layer. Each test pad has a probe mark. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a top surface away from the test pads. Multiple bond pads are disposed in and exposed outside the second dielectric layer. Each bond pad is electrically connected to the corresponding test pad. The bond pads have bonding surfaces away from the test pads. The bonding surfaces are flush with the top surface. In the normal direction of the substrate structure, each bond pad does not overlap the probe mark of the corresponding test pad.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first electrode layer disposed on the substrate, a gate electrode layer disposed on the first electrode layer, a second electrode layer disposed on the gate electrode layer, an oxide semiconductor layer penetrating through the gate electrode layer, a gate dielectric layer disposed between the gate electrode layer and the oxide semiconductor layer, a first insulating layer disposed between the gate electrode layer and the first electrode layer, and a second insulating layer disposed between the gate electrode layer and the second electrode layer. The oxide semiconductor layer is in direct contact with the first electrode layer and the second electrode layer, respectively.

Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.

Abstract: The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element

Abstract: A manufacturing method of a SRAM memory device includes forming two transistors on a substrate, forming an inner dielectric layer covering the two transistors, forming contacts in the inner dielectric layer for coupling to source nodes of the two transistors, forming a metal interconnect structure on the inner dielectric layer, wherein a portion of an n-th metal layer of the metal interconnect structure is utilized as a lower metal layer, wherein n?1. An opening is formed in the metal interconnect structure to expose the lower metal layer, and then a capacitor is formed in the opening. The capacitor includes the lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The upper metal layer is a portion of an m-th metal layer of the metal interconnect structure, wherein m?n+1.

Abstract: A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation.

Abstract: A semiconductor package including a chip stack structure, a redistribution layer (RDL) structure and conductive plugs is provided. The chip stack structure includes stacked chips. Each of the chips includes a pad. The pads on the chips are located on the same side of the chip stack structure. The RDL structure is disposed on the first sidewall of the chip stack structure and adjacent to the pads. The conductive plugs penetrate through the RDL structure. The conductive plug is connected to the corresponding pad.

Abstract: The disclosure provides a wafer searching method and device. The method includes: obtaining a target wafer and a reference wafer; determining a first specific area in the target wafer, and obtaining a first significant distribution feature of the first specific area; determining a second specific area in the reference wafer, and obtaining a second significant distribution feature of the second specific area; in response to determining that the first significant distribution feature corresponds to the second significant distribution feature, estimating a fail pattern similarity between the first specific area and the second specific area; in response to determining that the fail pattern similarity is greater than a threshold, providing the reference wafer as a search result corresponding to the target wafer.

Abstract: A semiconductor package including a substrate, interposers, chips, and a dummy interposer is provided. The interposers are stacked on the substrate. The chips are located on the interposers. The chip is electrically connected to the interposer. The dummy interposer is located between the interposer and the substrate and is electrically connected to the interposer. The chip is not located between the dummy interposer and the interposer.

Abstract: A semiconductor device including a substrate and a capacitor is provided. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The first electrode has a plurality of hemispherical recesses. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. Surfaces of the hemispherical recesses are in direct contact with the insulating layer.

Abstract: A computer-implemented method of performing voltage rule check in an electronic design automation (EDA) platform is provided in the present invention, including steps of inserting pseudo device with safe operating area (SOA) model setting in a netlist generated by the EDA platform or in a schematic of process design kit (PDK), wherein parameters of the pseudo device and the model are set so that the pseudo device would not affect original circuits in the netlist and the schematic, performing SOA check in the netlist or the schematic through the EDA platform, and examining the warning messages triggered by the pseudo device and the model violating the SOA setting in the SOA check to find out layout sections violating the SOA setting.

Abstract: A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

Abstract: A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.