Abstract: A method for fabricating a shield gate MOSFET includes forming an epitaxial layer having a first conductivity type, forming a plurality of trenches in the epitaxial layer, forming a first and a second doped regions in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type. An insulating layer and a conductive layer as a shield gate are orderly formed in each of the trenches, and a portion of the conductive layer and the insulating layer are removed to expose a portion of the epitaxial layer in the trenches. An inter-gate oxide layer and a gate oxide layer are formed in the trenches, and a control gate is formed on the inter-gate oxide layer in the plurality of trenches.

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a plurality of active regions, a gate insulation layer, and a gate electrode. The active regions are defined by an isolation structure, wherein the active regions include a channel portion and two side portions, the channel portion has first opposite sides and second opposite sides, and the two side portions are at the first opposite sides of the channel portion. The gate insulation layer is disposed on a surface of the channel portion. The gate electrode is disposed on the gate insulation layer and extending on a portion of the isolation structure, wherein the gate electrode includes a pair of channel edge openings and a plurality of slits. The pair of channel edge openings are at the second opposite sides of the channel portion to expose a portion of the gate insulation layer, and the slits are disposed over the channel portion.

Abstract: A semiconductor structure including a substrate, a first isolation structure and a capacitor is provided. The substrate includes a capacitor region. The first isolation structure is disposed in the substrate in the capacitor region. The capacitor is located in the capacitor region. The capacitor includes the substrate in the capacitor region, an electrode layer and a first dielectric layer. The electrode layer is disposed in the substrate in the capacitor region. The first dielectric layer is disposed between the electrode layer and the substrate and between the electrode layer and the first isolation structure. The first dielectric layer is in direct contact with the first isolation structure.

Abstract: An interconnect structure including a dielectric structure, plugs, and conductive lines is provided. The dielectric structure is disposed on a substrate. The plugs are disposed in the dielectric structure. The conductive lines are disposed in the dielectric structure and are electrically connected to the plugs. The sidewall of at least one of the conductive lines is in direct contact with the dielectric structure.

Abstract: A CMOS image sensor with 3D monolithic OSFET and FEMIM capacitor, including a substrate with CMOS devices formed thereon, a BEOL interconnect layer on the substrate and with BEOL interconnects formed therein, a pixel circuit layer on the BEOL interconnect layer. The OSFETs and FEMIM capacitors are formed in the pixel circuit layer, and a photoelectric conversion layer on the pixel circuit layer and with photodiodes are formed therein, wherein the CMOS devices, the OSFETs, FEMIM capacitors and photodiodes are electrically connected with each other through the BEOL interconnects.

Abstract: A capacitor structure including a silicon material layer, a support frame layer, and a capacitor is provided. The support frame layer is disposed in the silicon material layer. The support frame layer has recesses. There is a cavity between two adjacent recesses. The support frame layer is located between the cavity and the recess. The support frame layer has a through hole directly above the cavity. The capacitor is disposed in the silicon material layer. The capacitor includes a first insulating layer and a first electrode layer. The first insulating layer is disposed on the support frame layer. The first electrode layer is disposed on the first insulating layer and fills the recess and the cavity.

Abstract: A memory device is provided. The memory device includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The data paths respectively correspond to the bit lines. The number of the data paths is equal to or less than the number of the bit lines. A plurality of data transmission ports of the logic chip are electrically connected to the data paths of the at least one memory chip in a one-to-one manner. The number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip.

Abstract: A memory structure including the following components is provided. A first dielectric layer is disposed on a substrate. A first memory cell includes a first conductive layer, a second conductive layer, a first channel layer, and a first charge storage layer. The first conductive layer and the second conductive layer are sequentially stacked on the first dielectric layer and are electrically insulated from each other. The first channel layer is disposed on one side of the first conductive layer and one side of the second conductive layer. The first charge storage layer is disposed between the first conductive layer and the first channel layer. A first bit line is disposed in the first dielectric layer and is connected to the first channel layer. A source line is disposed above the first channel layer and is connected to the first channel layer.

Abstract: Provided is a method for generating a chip probing wafer map, and the method includes: obtaining test data associated with a first chip, wherein the first chip includes a plurality of sequentially arranged first dies, and each of the first dies belongs to one of a plurality of bin numbers; assigning different predetermined color codes to the bin numbers; and generating a first general chip probing wafer map for the first chip by assigning a color code of each of the first dies as a corresponding predetermined color code according to the bin number to which each of the first dies belongs.

Abstract: A capacitor integrated structure, a capacitor unit and a manufacturing process thereof are provided. The manufacturing process of capacitor units includes the steps of: forming a plurality of capacitor stacking structures on a substrate having an insulation layer thereon; performing a first cut on insulation dividers provided between the adjacent capacitor stacking structures to form a plurality of recesses that expose first conductive portion and second conductive portion of each of the capacitor stacking structures; filling a metallic material in the recesses to form a plurality of metallic dividers that are electrically connected to the first conductive portion and the second conductive portion of each of the capacitor stacking structures; performing a second cut on the metallic dividers to form a plurality of independent capacitor units; and forming metallic walls on two opposite sides of each of the capacitor units, so as to provide a capacitor unit having two end electrodes.

Abstract: An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.

Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.

Abstract: A semiconductor structure including a substrate, a through-substrate via (TSV), a first insulating layer, an isolation structure, and a capacitor is provided. The substrate includes a TSV region and a keep-out zone (KOZ) adjacent to each other. The TSV is located in the substrate in the TSV region. The first insulating layer is located between the TSV and the substrate. The isolation structure is located in the substrate in the KOZ. There are trenches in the isolation structure. A capacitor is located on the isolation structure and in the trenches.

Abstract: Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a first dielectric layer, a first gate, a second dielectric layer, and a second gate. The first dielectric layer is located on the substrate. The first gate is located on the first dielectric layer. The second dielectric layer is located on the substrate. The second gate is located on the second dielectric layer. A bottom surface of the second gate and a bottom surface of the first gate are located on different planes.

Abstract: The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element.

Abstract: A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer. An opening is formed in the stack structure. A gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer. A second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.

Abstract: A memory structure including a substrate and memory cells is provided. The memory cells are stacked on the substrate. Each memory cell includes a first conductive layer, a first gate, a second gate, a second conductive layer, a channel layer, and a first charge storage layer. The first conductive layer, the first gate, the second gate, and the second conductive layer are sequentially stacked. The first conductive layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductive layer are electrically insulated from each other. The first gate and the second gate are electrically insulated from the channel layer. The first conductive layer and the second conductive layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

Abstract: A method of improving endurance of a NOR flash is provided. The NOR flash includes a substrate, a well formed in the substrate, a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate sequentially stacked on the substrate, and a source and a drain formed in the well. The method includes the following steps. An erase time of the NOR flash is detected. In the case where the erase time exceeds a predetermined value, the source is brought into a floating state, a negative voltage is applied to the control gate, and a positive voltage is applied to the well to perform Joule heating on a drain side.

Abstract: A vertical oxide-semiconductor transistor is proposed by the present invention, including an insulating substrate, a source in the insulating substrate, a gate on the insulating substrate, wherein the gate surrounds the source and forms a recess on the source, an inner spacer on an inner sidewall of the gate in the recess, an oxide-semiconductor layer on the inner spacer and the source and directly contacts the source, a filling oxide on the oxide-semiconductor layer and filling in the recess, and a drain on the oxide-semiconductor layer and filling oxide and directly connecting with the oxide-semiconductor layer, wherein the drain completely covers the source and partially overlaps the gate.

Abstract: A planarization method including the following steps is provided. A substrate is provided. The substrate includes a first region and a second region. A material layer is formed on the substrate. The top surface of the material layer in the first region is lower than the top surface of the material layer in the second region. A patterned photoresist layer is formed on the material layer in the first region. A first etching process is performed on the patterned photoresist layer, so that the top surface of the patterned photoresist layer and the top surface of the material layer in the second region have substantially the same height. A second etching process is performed on the patterned photoresist layer and the material layer. In the second etching process, the etching rate of the patterned photoresist layer is substantially the same as the etching rate of the material layer.